From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57550) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4QwB-0008J5-TD for qemu-devel@nongnu.org; Mon, 15 Jun 2015 05:44:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4Qw4-0000Sn-1P for qemu-devel@nongnu.org; Mon, 15 Jun 2015 05:44:13 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50581) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Qw3-0000SR-T8 for qemu-devel@nongnu.org; Mon, 15 Jun 2015 05:44:07 -0400 Date: Mon, 15 Jun 2015 11:43:58 +0200 From: "Michael S. Tsirkin" Message-ID: <20150615114145-mutt-send-email-mst@redhat.com> References: <55799751.1030904@redhat.com> <20150611142425.GA10763@morn.localdomain> <55799CD6.1060506@redhat.com> <20150611165404.GB20655@morn.localdomain> <5579C959.8020607@redhat.com> <20150611191058.GA28252@morn.localdomain> <1434088832.28479.7.camel@redhat.com> <557ACDD7.9060801@redhat.com> <20150612132329.GB3622@morn.localdomain> <1434348068.31654.15.camel@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1434348068.31654.15.camel@redhat.com> Subject: Re: [Qemu-devel] [PATCH V2] pci: fixes to allow booting from extra root pci buses. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: Marcel Apfelbaum , lersek@redhat.com, Kevin O'Connor , seabios@seabios.org, qemu-devel@nongnu.org On Mon, Jun 15, 2015 at 08:01:08AM +0200, Gerd Hoffmann wrote: > On Fr, 2015-06-12 at 09:23 -0400, Kevin O'Connor wrote: > > On Fri, Jun 12, 2015 at 03:17:27PM +0300, Marcel Apfelbaum wrote: > > > On 06/12/2015 09:00 AM, Gerd Hoffmann wrote: > > > >>On each boot, coreboot might decide to assign a different bus id to > > > >>the extra roots (for example, if a device with a PCI bridge is > > > >>inserted and it's bus allocation causes bus ids to shift). > > > >>Technically, coreboot could even change the order extra buses are > > > >>assigned bus ids, but doesn't today. > > > >> > > > >>This was seen on several AMD systems - I'm told at least some Intel > > > >>systems have multiple root buses, but the bus numbers are just hard > > > >>wired. > > > > > > > >This is how the qemu pxb works: root bus numbers are a config option for > > > >the root bridge device, i.e. from the guest point of view they are > > > >hard-wired. > > > Exactly. In our case, the HW assigns the PXB bus bumber, and again, > > > I saw this also on real HW with multiple buses, the bus nr comes > > > from ACPI, meaning the vendor. > > > > I'm confused where ACPI comes into this. In all cases I know of, the > > firmware generates the ACPI tables to match the hardware. I've never > > heard of hardware configuring itself from the ACPI tables. > > We have basically the same model in qemu, except that it isn't the > firmware but qemu generating the tables (and qemu looks at the registers > programmed by the firmware to make sure things match). > > The pxb has no registers to program, the hardware just shows up on a bus > number (qemu cfg, hard-wired for the guest). ACPI must specify it so > the guest OS finds it. When passing bus numbers via fw_cfg the must > match acpi of course. > > I'm wondering whenever things become easier if we add config registers > to the pxb, where the firmware can program the bus number range and we > can use the config register base as a way to specify which pxb we are > referring to ? > > cheers, > Gerd > But then we'll need a bunch of fw cfg entries to let guest discover the extra roots and their bus ranges. -- MST