From: Aurelien Jarno <aurelien@aurel32.net>
To: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: leon.alrae@imgtec.com, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] disas/mips: fix disassembling R6 instructions
Date: Wed, 1 Jul 2015 16:32:28 +0200 [thread overview]
Message-ID: <20150701143228.GR931@aurel32.net> (raw)
In-Reply-To: <1435678395-14576-1-git-send-email-yongbok.kim@imgtec.com>
On 2015-06-30 16:33, Yongbok Kim wrote:
> In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF
> and CACHE instructions have 9 bits offsets.
>
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
> ---
> disas/mips.c | 12 ++++++------
> 1 files changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2015-07-01 14:32 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-30 15:33 [Qemu-devel] [PATCH] disas/mips: fix disassembling R6 instructions Yongbok Kim
2015-07-01 14:32 ` Aurelien Jarno [this message]
2015-07-08 13:43 ` Leon Alrae
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