From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48981) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZAWze-00050b-7J for qemu-devel@nongnu.org; Thu, 02 Jul 2015 01:25:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZAWza-00056M-7p for qemu-devel@nongnu.org; Thu, 02 Jul 2015 01:25:02 -0400 Received: from mail-lb0-x22c.google.com ([2a00:1450:4010:c04::22c]:36392) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZAWzZ-000567-Uk for qemu-devel@nongnu.org; Thu, 02 Jul 2015 01:24:58 -0400 Received: by lbbpo10 with SMTP id po10so25106165lbb.3 for ; Wed, 01 Jul 2015 22:24:56 -0700 (PDT) Date: Thu, 2 Jul 2015 08:31:34 +0300 From: Antony Pavlov Message-Id: <20150702083134.6ee193b130cc4e1922a6e74d@gmail.com> In-Reply-To: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH pic32 v2 0/5] Support for Microchip pic32mx7 and pic32mz microcontrollers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Serge Vakulenko Cc: Leon Alrae , qemu-devel@nongnu.org, Aurelien Jarno On Tue, 30 Jun 2015 21:12:29 -0700 Serge Vakulenko wrote: > Please find below a set of patches, which allow to simulate Microchip PIC= 32 > microcontrollers on QEMU. For examples of real PIC32 applications running > on QEMU, see page: https://github.com/sergev/qemu/wiki >=20 > (1) Make the CPU clock frequency configurable per platform. > Currently the clock rate for all MIPS platforms is fixed at 100MHz. > Need to make it 40MHz for pic32mx7. >=20 > (2) For TLBWR instruction, the generated random index value has been not > quite random and did not take into account the Wired register value. = Fixed. >=20 > (3) Added support for external interrupt controller mode (EIC). > Required for pic32. >=20 > (4) Added two processor variants: M4K and microAptivUP. > Needed for pic32mx and pic32mz simulation. >=20 > (5) Added two machine platforms: Microchip pic32mx7 and pic32mz > microcontrollers. Several board types supported for each platform: >=20 > pic32mx7-explorer16 PIC32MX7 microcontroller on Microchip Explorer-1= 6 board > pic32mx7-max32 PIC32MX7 microcontroller on chipKIT Max32 board > pic32mx7-maximite PIC32MX7 microcontroller on Geoff's Maximite com= puter > pic32mz-explorer16 PIC32MZ microcontroller on Microchip Explorer-16= board > pic32mz-meb2 PIC32MZ microcontroller on Microchip MEB-II board > pic32mz-wifire PIC32MZ microcontroller on chipKIT WiFire board >=20 >=20 > Serge Vakulenko (5): > Speed of MIPS CPU timer made configurable per platform. > Fixed random index generation for TLBWR instruction. It was not quite > random and did not skip Wired entries. > Added support for external interrupt controller (EIC) mode. > Two new processor variants: M4K and microAptivP. > Two new machine platforms: pic32mz7 and pic32mz. Please fix your subject lines according to "Write a good commit message" se= ction of http://wiki.qemu.org/Contribute/SubmitAPatch. Also please use the imperative mood in the subject line. --=A0 Best regards, =A0 Antony Pavlov