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From: Aurelien Jarno <aurelien@aurel32.net>
To: Serge Vakulenko <serge.vakulenko@gmail.com>
Cc: Leon Alrae <leon.alrae@imgtec.com>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH pic32 v3 01/16] pic32: make the CPU clock frequency configurable per platform
Date: Mon, 6 Jul 2015 10:42:34 +0200	[thread overview]
Message-ID: <20150706084234.GV931@aurel32.net> (raw)
In-Reply-To: <1436163304-6167-2-git-send-email-serge.vakulenko@gmail.com>

On 2015-07-05 23:14, Serge Vakulenko wrote:
> Currently the clock rate for all MIPS platforms is fixed at 100MHz.
> Need to make it 40MHz for pic32mx7.
> 
> Signed-off-by: Serge Vakulenko <serge.vakulenko@gmail.com>
> ---
>  hw/mips/cputimer.c        | 15 +++++++--------
>  hw/mips/mips_fulong2e.c   |  2 +-
>  hw/mips/mips_jazz.c       |  2 +-
>  hw/mips/mips_malta.c      |  4 ++--
>  hw/mips/mips_mipssim.c    |  2 +-
>  hw/mips/mips_r4k.c        |  2 +-
>  include/hw/mips/cpudevs.h |  2 +-
>  target-mips/cpu.h         |  1 +
>  8 files changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer.c
> index 577c9ae..75917cf 100644
> --- a/hw/mips/cputimer.c
> +++ b/hw/mips/cputimer.c
> @@ -25,8 +25,6 @@
>  #include "qemu/timer.h"
>  #include "sysemu/kvm.h"
>  
> -#define TIMER_FREQ	100 * 1000 * 1000
> -
>  /* XXX: do not use a global */
>  uint32_t cpu_mips_get_random (CPUMIPSState *env)
>  {
> @@ -50,8 +48,8 @@ static void cpu_mips_timer_update(CPUMIPSState *env)
>  
>      now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
>      wait = env->CP0_Compare - env->CP0_Count -
> -	    (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
> -    next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
> +        (uint32_t)muldiv64(now, env->count_freq, get_ticks_per_sec());
> +    next = now + muldiv64(wait, get_ticks_per_sec(), env->count_freq);
>      timer_mod(env->timer, next);
>  }
>  
> @@ -80,7 +78,7 @@ uint32_t cpu_mips_get_count (CPUMIPSState *env)
>          }
>  
>          return env->CP0_Count +
> -            (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
> +            (uint32_t)muldiv64(now, env->count_freq, get_ticks_per_sec());
>      }
>  }
>  
> @@ -97,7 +95,7 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
>          /* Store new count register */
>          env->CP0_Count =
>              count - (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
> -                                       TIMER_FREQ, get_ticks_per_sec());
> +                                       env->count_freq, get_ticks_per_sec());
>          /* Update timer timer */
>          cpu_mips_timer_update(env);
>      }
> @@ -122,7 +120,7 @@ void cpu_mips_stop_count(CPUMIPSState *env)
>  {
>      /* Store the current value */
>      env->CP0_Count += (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
> -                                         TIMER_FREQ, get_ticks_per_sec());
> +                                         env->count_freq, get_ticks_per_sec());
>  }
>  
>  static void mips_timer_cb (void *opaque)
> @@ -145,7 +143,7 @@ static void mips_timer_cb (void *opaque)
>      env->CP0_Count--;
>  }
>  
> -void cpu_mips_clock_init (CPUMIPSState *env)
> +void cpu_mips_clock_init(CPUMIPSState *env, unsigned count_freq)
>  {
>      /*
>       * If we're in KVM mode, don't create the periodic timer, that is handled in
> @@ -153,5 +151,6 @@ void cpu_mips_clock_init (CPUMIPSState *env)
>       */
>      if (!kvm_enabled()) {
>          env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
> +        env->count_freq = count_freq;
>      }
>  }

As said in my other email, you should check that the requested frequency
is 100MHz in KVM mode, for example with an assert.

Otherwise looks fine.

> diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c
> index dea941a..5decc30 100644
> --- a/hw/mips/mips_fulong2e.c
> +++ b/hw/mips/mips_fulong2e.c
> @@ -343,7 +343,7 @@ static void mips_fulong2e_init(MachineState *machine)
>  
>      /* Init internal devices */
>      cpu_mips_irq_init_cpu(env);
> -    cpu_mips_clock_init(env);
> +    cpu_mips_clock_init(env, 100*1000*1000);
>  
>      /* North bridge, Bonito --> IP2 */
>      pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));
> diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c
> index 9d60633..02629fa 100644
> --- a/hw/mips/mips_jazz.c
> +++ b/hw/mips/mips_jazz.c
> @@ -210,7 +210,7 @@ static void mips_jazz_init(MachineState *machine,
>  
>      /* Init CPU internal devices */
>      cpu_mips_irq_init_cpu(env);
> -    cpu_mips_clock_init(env);
> +    cpu_mips_clock_init(env, 100*1000*1000);
>  
>      /* Chipset */
>      rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 3082e75..0393017 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -988,7 +988,7 @@ void mips_malta_init(MachineState *machine)
>  
>          /* Init internal devices */
>          cpu_mips_irq_init_cpu(env);
> -        cpu_mips_clock_init(env);
> +        cpu_mips_clock_init(env, 100*1000*1000);
>          qemu_register_reset(main_cpu_reset, cpu);
>      }
>      cpu = MIPS_CPU(first_cpu);
> @@ -1144,7 +1144,7 @@ void mips_malta_init(MachineState *machine)
>  
>      /* Init internal devices */
>      cpu_mips_irq_init_cpu(env);
> -    cpu_mips_clock_init(env);
> +    cpu_mips_clock_init(env, 100*1000*1000);
>  
>      /*
>       * We have a circular dependency problem: pci_bus depends on isa_irq,
> diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c
> index 61f74a6..940ca58 100644
> --- a/hw/mips/mips_mipssim.c
> +++ b/hw/mips/mips_mipssim.c
> @@ -213,7 +213,7 @@ mips_mipssim_init(MachineState *machine)
>  
>      /* Init CPU internal devices. */
>      cpu_mips_irq_init_cpu(env);
> -    cpu_mips_clock_init(env);
> +    cpu_mips_clock_init(env, 100*1000*1000);
>  
>      /* Register 64 KB of ISA IO space at 0x1fd00000. */
>      memory_region_init_alias(isa, NULL, "isa_mmio",
> diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c
> index f4dcacd..5f0b766 100644
> --- a/hw/mips/mips_r4k.c
> +++ b/hw/mips/mips_r4k.c
> @@ -266,7 +266,7 @@ void mips_r4k_init(MachineState *machine)
>  
>      /* Init CPU internal devices */
>      cpu_mips_irq_init_cpu(env);
> -    cpu_mips_clock_init(env);
> +    cpu_mips_clock_init(env, 100*1000*1000);
>  
>      /* ISA bus: IO space at 0x14000000, mem space at 0x10000000 */
>      memory_region_init_alias(isa_io, NULL, "isa-io",
> diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h
> index b2626f2..4d4e62a 100644
> --- a/include/hw/mips/cpudevs.h
> +++ b/include/hw/mips/cpudevs.h
> @@ -12,6 +12,6 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
>  void cpu_mips_irq_init_cpu(CPUMIPSState *env);
>  
>  /* mips_timer.c */
> -void cpu_mips_clock_init(CPUMIPSState *);
> +void cpu_mips_clock_init(CPUMIPSState *, unsigned count_freq);
>  
>  #endif
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 474a0e3..c476166 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -595,6 +595,7 @@ struct CPUMIPSState {
>      const mips_def_t *cpu_model;
>      void *irq[8];
>      QEMUTimer *timer; /* Internal timer */
> +    unsigned count_freq; /* rate of Count register */
>  };
>  
>  #include "cpu-qom.h"
> -- 
> 2.2.2
> 
> 

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net

  reply	other threads:[~2015-07-06  8:42 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-06  6:14 [Qemu-devel] [PATCH pic32 v3 00/16] add support for pic32 microcontrollers Serge Vakulenko
2015-07-06  6:14 ` [Qemu-devel] [PATCH pic32 v3 01/16] pic32: make the CPU clock frequency configurable per platform Serge Vakulenko
2015-07-06  8:42   ` Aurelien Jarno [this message]
2015-07-06  6:14 ` [Qemu-devel] [PATCH pic32 v3 02/16] pic32: use LCG algorithm for generated random index of TLBWR instruction Serge Vakulenko
2015-07-06  8:43   ` Aurelien Jarno
2015-09-15  9:46   ` Leon Alrae
2015-07-06  6:14 ` [Qemu-devel] [PATCH pic32 v3 03/16] pic32: add support for external interrupt controller mode (EIC) Serge Vakulenko
2015-07-06  9:34   ` Aurelien Jarno
2015-07-06  6:14 ` [Qemu-devel] [PATCH pic32 v3 04/16] pic32: add two MIPS processor variants: M4K and microAptivUP Serge Vakulenko
2015-07-06  9:35   ` Aurelien Jarno
2015-10-02 10:37   ` Leon Alrae
2015-07-06  6:14 ` [Qemu-devel] [PATCH pic32 v3 05/16] pic32: add file pic32_peripherals.h Serge Vakulenko
2015-07-06  8:02   ` Peter Crosthwaite
2015-07-06  9:01   ` Aurelien Jarno
2015-07-06 17:04     ` Peter Crosthwaite
2015-07-06  6:14 ` [Qemu-devel] [PATCH pic32 v3 06/16] pic32: add file pic32mx.h Serge Vakulenko
2015-07-06  6:14 ` [Qemu-devel] [PATCH pic32 v3 07/16] pic32: add file pic32mz.h Serge Vakulenko
2015-07-06  6:14 ` [Qemu-devel] [PATCH pic32 v3 08/16] pic32: add file mips_pic32mx7.c Serge Vakulenko
2015-07-06 11:18   ` Antony Pavlov
2015-07-06  6:14 ` [Qemu-devel] [PATCH pic32 v3 09/16] pic32: add file mips_pic32mz.c Serge Vakulenko
2015-07-06  6:14 ` [Qemu-devel] [PATCH pic32 v3 10/16] pic32: add file pic32_load_hex.c Serge Vakulenko
2015-07-06  6:14 ` [Qemu-devel] [PATCH pic32 v3 11/16] pic32: add file pic32_uart.c Serge Vakulenko
2015-07-06  8:08   ` Peter Crosthwaite
2015-07-06  6:15 ` [Qemu-devel] [PATCH pic32 v3 12/16] pic32: add file pic32_gpio.c Serge Vakulenko
2015-07-06  6:15 ` [Qemu-devel] [PATCH pic32 v3 13/16] pic32: add file pic32_spi.c Serge Vakulenko
2015-07-06  7:58   ` Peter Crosthwaite
2015-07-06  6:15 ` [Qemu-devel] [PATCH pic32 v3 14/16] pic32: add file pic32_sdcard.c Serge Vakulenko
2015-07-06  8:05   ` Peter Crosthwaite
2015-07-06  6:15 ` [Qemu-devel] [PATCH pic32 v3 15/16] pic32: add file pic32_ethernet.c Serge Vakulenko
2015-07-06  6:15 ` [Qemu-devel] [PATCH pic32 v3 16/16] pic32: update makefiles to cover pic32 support Serge Vakulenko

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