From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57402) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZC4ON-0006hh-Fg for qemu-devel@nongnu.org; Mon, 06 Jul 2015 07:16:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZC4OJ-0006TI-Nh for qemu-devel@nongnu.org; Mon, 06 Jul 2015 07:16:55 -0400 Date: Mon, 6 Jul 2015 21:13:43 +1000 From: David Gibson Message-ID: <20150706111343.GG17857@voom.redhat.com> References: <1436148670-6592-1-git-send-email-aik@ozlabs.ru> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="AGZzQgpsuUlWC1xT" Content-Disposition: inline In-Reply-To: <1436148670-6592-1-git-send-email-aik@ozlabs.ru> Subject: Re: [Qemu-devel] [PATCH qemu v10 00/14] spapr: vfio: Enable Dynamic DMA windows (DDW) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy Cc: Michael Roth , Alex Williamson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Gavin Shan --AGZzQgpsuUlWC1xT Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jul 06, 2015 at 12:10:56PM +1000, Alexey Kardashevskiy wrote: >=20 > (cut-n-paste from kernel patchset) >=20 > Each Partitionable Endpoint (IOMMU group) has an address range on a PCI b= us > where devices are allowed to do DMA. These ranges are called DMA windows. > By default, there is a single DMA window, 1 or 2GB big, mapped at zero > on a PCI bus. >=20 > PAPR defines a DDW RTAS API which allows pseries guests > querying the hypervisor about DDW support and capabilities (page size mask > for now). A pseries guest may request an additional (to the default) > DMA windows using this RTAS API. > The existing pseries Linux guests request an additional window as big as > the guest RAM and map the entire guest window which effectively creates > direct mapping of the guest memory to a PCI bus. >=20 > This patchset reworks PPC64 IOMMU code and adds necessary structures > to support big windows. >=20 > Once a Linux guest discovers the presence of DDW, it does: > 1. query hypervisor about number of available windows and page size masks; > 2. create a window with the biggest possible page size (today 4K/64K/16M); > 3. map the entire guest RAM via H_PUT_TCE* hypercalls; > 4. switche dma_ops to direct_dma_ops on the selected PE. >=20 > Once this is done, H_PUT_TCE is not called anymore for 64bit devices and > the guest does not waste time on DMA map/unmap operations. >=20 > Note that 32bit devices won't use DDW and will keep using the default > DMA window so KVM optimizations will be required (to be posted later). >=20 > This patchset adds DDW support for pseries. The host kernel changes are > required, available in the current upstream. >=20 > This patchset is based on git://github.com/dgibson/qemu.git spapr-next br= anch. >=20 > Please comment. Thanks! I've applied this to my "spapr-dev" branch. Here's what needs to happen before I move it into spapr-next (which is what I'll be pushing to Alex Graf). * For you and Gavin to test it to see that DDW and EEH work properly together * Some word from Alex W on how he wants to go about merging 12-13/14 * Some indication about who should be merging 2/14 * Review from at least one more person - I've looked at so many versions of the ddw patches I no longer trust that I've got it all straight in my head --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --AGZzQgpsuUlWC1xT Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJVmmLnAAoJEGw4ysog2bOShrwP/0RAqvIZfrCf7Rl8hSY9+V2a JceBWsBt4v1ALkeAe+PrHmViWYKsjiqrycqt4cyd4fJ7u6rdsIIkCkvtVBhqKqzV j20QN/8HioCbWeS5wSAkMkNN63MJGewzs9qFw2cf/plMZoCepVZdc8cKt/1D+1GJ 1/xMeIU/Ka9ItouxY0FWxobhRNCP3jYGqp1FpsawaShR+uy7C4c8mmSu6ogoRvJt Kduma3WoF5bRfpzngHo9RZ1Ab/uxRPbihMBoGNpXTUgJF1r4SPWFwu9Dybarv34A f3wNiUbTy7cK/qxY3sUwJQfmtOkvkKKuY77Oc4ILMr8vYwQi/wa36rtMO5z9Yrbi cdmjZdMe01zIb0yLUDREownZqI3Y7JrX7V4dXQNUnA94qNDfHldJ+PFiVH2l94jz x8NoCeaw7dDbmpjVO67iZX/8SfeV16XBJTRjcCf5MCueTZDlwRJt5EF0L7VMhyLd m0wAX5PVZVFGQK+tI5NaMLfSnjRn7da/0t7fjFkeux/LBnOe/gJvNaTlzC3eL0iV vKwKziDl+K45SMb49s0w5+TYL1sh92oJaGdaKtpTzxQtQVwqNLsBXogDaJi0FIdC gfbXlg/33zLAyF0RgIcF+34zZmzdx8yrKV/70ZOsuB7OzCczhLPQGY7GVMdpXER0 5AZgSFtOq3GBDIWicixq =G1Pp -----END PGP SIGNATURE----- --AGZzQgpsuUlWC1xT--