* [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03
@ 2015-07-03 20:47 Eduardo Habkost
2015-07-03 20:47 ` [Qemu-devel] [PULL 1/3] i386: Introduce ARAT CPU feature Eduardo Habkost
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Eduardo Habkost @ 2015-07-03 20:47 UTC (permalink / raw)
To: qemu-devel, Peter Maydell
Cc: Paolo Bonzini, Andreas Färber, Richard Henderson
The following changes since commit 35360642d043c2a5366e8a04a10e5545e7353bd5:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-20150703-1' into staging (2015-07-03 12:05:31 +0100)
are available in the git repository at:
git://github.com/ehabkost/qemu.git tags/x86-pull-request
for you to fetch changes up to de9a6f1c8ab4fcfd9927da5ae28e75efe10f721c:
target-i386: emulate CPUID level of real hardware (2015-07-03 17:38:25 -0300)
----------------------------------------------------------------
X86 queue, 2015-07-03
----------------------------------------------------------------
Jan Kiszka (1):
i386: Introduce ARAT CPU feature
Paolo Bonzini (1):
target-i386: avoid overflow in the tsc-frequency property
Radim Krčmář (1):
target-i386: emulate CPUID level of real hardware
include/hw/compat.h | 70 +++++++++++++++++++++++++++++++++++++++++++++++++++-
include/hw/i386/pc.h | 7 +++++-
target-i386/cpu.c | 70 +++++++++++++++++++++++++++++++++++++---------------
target-i386/cpu.h | 5 +++-
target-i386/kvm.c | 2 ++
5 files changed, 131 insertions(+), 23 deletions(-)
--
2.1.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [Qemu-devel] [PULL 1/3] i386: Introduce ARAT CPU feature 2015-07-03 20:47 [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 Eduardo Habkost @ 2015-07-03 20:47 ` Eduardo Habkost 2015-07-03 20:47 ` [Qemu-devel] [PULL 2/3] target-i386: avoid overflow in the tsc-frequency property Eduardo Habkost ` (3 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: Eduardo Habkost @ 2015-07-03 20:47 UTC (permalink / raw) To: qemu-devel, Peter Maydell Cc: Paolo Bonzini, Jan Kiszka, Andreas Färber, Richard Henderson From: Jan Kiszka <jan.kiszka@siemens.com> ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- include/hw/i386/pc.h | 7 ++++++- target-i386/cpu.c | 33 ++++++++++++++++++++++++++++++++- target-i386/cpu.h | 3 +++ target-i386/kvm.c | 2 ++ 4 files changed, 43 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 86c5651..bbd0bb0 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -293,7 +293,12 @@ int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); #define PC_COMPAT_2_3 \ - HW_COMPAT_2_3 + HW_COMPAT_2_3 \ + {\ + .driver = TYPE_X86_CPU,\ + .property = "arat",\ + .value = "off",\ + }, #define PC_COMPAT_2_2 \ PC_COMPAT_2_3 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 36b07f9..b4f9461 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -286,6 +286,17 @@ static const char *cpuid_xsave_feature_name[] = { NULL, NULL, NULL, NULL, }; +static const char *cpuid_6_feature_name[] = { + NULL, NULL, "arat", NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +}; + #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) @@ -341,6 +352,7 @@ static const char *cpuid_xsave_feature_name[] = { CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED */ #define TCG_APM_FEATURES 0 +#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT typedef struct FeatureWordInfo { @@ -410,6 +422,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .cpuid_reg = R_EAX, .tcg_features = 0, }, + [FEAT_6_EAX] = { + .feat_names = cpuid_6_feature_name, + .cpuid_eax = 6, .cpuid_reg = R_EAX, + .tcg_features = TCG_6_EAX_FEATURES, + }, }; typedef struct X86RegisterInfo32 { @@ -1003,6 +1020,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", }, @@ -1032,6 +1051,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Xeon E312xx (Sandy Bridge)", }, @@ -1064,6 +1085,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", }, @@ -1098,6 +1121,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Haswell, no TSX)", }, { @@ -1132,6 +1157,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_RTM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Haswell)", }, @@ -1168,6 +1195,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Broadwell, no TSX)", }, @@ -1204,6 +1233,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Broadwell)", }, @@ -2359,7 +2390,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 6: /* Thermal and Power Leaf */ - *eax = 0; + *eax = env->features[FEAT_6_EAX]; *ebx = 0; *ecx = 0; *edx = 0; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 603aaf0..d2eaea8 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -414,6 +414,7 @@ typedef enum FeatureWord { FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ FEAT_SVM, /* CPUID[8000_000A].EDX */ FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ + FEAT_6_EAX, /* CPUID[6].EAX */ FEATURE_WORDS, } FeatureWord; @@ -579,6 +580,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_XSAVE_XGETBV1 (1U << 2) #define CPUID_XSAVE_XSAVES (1U << 3) +#define CPUID_6_EAX_ARAT (1U << 2) + /* CPUID[0x80000007].EDX flags: */ #define CPUID_APM_INVTSC (1U << 8) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index daced5c..96c8d03 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -232,6 +232,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, if (!kvm_irqchip_in_kernel()) { ret &= ~CPUID_EXT_X2APIC; } + } else if (function == 6 && reg == R_EAX) { + ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */ } else if (function == 0x80000001 && reg == R_EDX) { /* On Intel, kvm returns cpuid according to the Intel spec, * so add missing bits according to the AMD spec: -- 2.1.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Qemu-devel] [PULL 2/3] target-i386: avoid overflow in the tsc-frequency property 2015-07-03 20:47 [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 Eduardo Habkost 2015-07-03 20:47 ` [Qemu-devel] [PULL 1/3] i386: Introduce ARAT CPU feature Eduardo Habkost @ 2015-07-03 20:47 ` Eduardo Habkost 2015-07-03 20:47 ` [Qemu-devel] [PULL 3/3] target-i386: emulate CPUID level of real hardware Eduardo Habkost ` (2 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: Eduardo Habkost @ 2015-07-03 20:47 UTC (permalink / raw) To: qemu-devel, Peter Maydell Cc: Paolo Bonzini, Andreas Färber, Richard Henderson From: Paolo Bonzini <pbonzini@redhat.com> The TSC frequency fits comfortably in an int when expressed in kHz, but it may overflow when converted to Hz. In this case, tsc-frequency returns a negative value because x86_cpuid_get_tsc_freq does a 32-bit multiplication before assigning to int64_t. For simplicity just make tsc_khz a 64-bit value. Spotted by Coverity. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target-i386/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index d2eaea8..bbeef22 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -961,7 +961,7 @@ typedef struct CPUX86State { uint8_t has_error_code; uint32_t sipi_vector; bool tsc_valid; - int tsc_khz; + int64_t tsc_khz; void *kvm_xsave_buf; uint64_t mcg_cap; -- 2.1.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Qemu-devel] [PULL 3/3] target-i386: emulate CPUID level of real hardware 2015-07-03 20:47 [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 Eduardo Habkost 2015-07-03 20:47 ` [Qemu-devel] [PULL 1/3] i386: Introduce ARAT CPU feature Eduardo Habkost 2015-07-03 20:47 ` [Qemu-devel] [PULL 2/3] target-i386: avoid overflow in the tsc-frequency property Eduardo Habkost @ 2015-07-03 20:47 ` Eduardo Habkost 2015-07-03 20:52 ` [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 Andreas Färber 2015-07-05 18:33 ` Peter Maydell 4 siblings, 0 replies; 10+ messages in thread From: Eduardo Habkost @ 2015-07-03 20:47 UTC (permalink / raw) To: qemu-devel, Peter Maydell Cc: Paolo Bonzini, Radim Krčmář, Andreas Färber, Richard Henderson From: Radim Krčmář <rkrcmar@redhat.com> W10 insider has a bug where it ignores CPUID level and interprets CPUID.(EAX=07H, ECX=0H) incorrectly, because CPUID in fact returned CPUID.(EAX=04H, ECX=0H); this resulted in execution of unsupported instructions. While it's a Windows bug, there is no reason to emulate incorrect level. I used http://instlatx64.atw.hu/ as a source of CPUID and checked that it matches Penryn Xeon X5472, Westmere Xeon W3520, SandyBridge i5-2540M, and Haswell i5-4670T. kvm64 and qemu64 were bumped to 0xD to allow all available features for them (and to avoid the same Windows bug). Signed-off-by: Radim Krčmář <rkrcmar@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- include/hw/compat.h | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++- target-i386/cpu.c | 37 ++++++++++++++-------------- 2 files changed, 87 insertions(+), 20 deletions(-) diff --git a/include/hw/compat.h b/include/hw/compat.h index 4a43466..55cfcd5 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -2,7 +2,75 @@ #define HW_COMPAT_H #define HW_COMPAT_2_3 \ - /* empty */ + {\ + .driver = "qemu64" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(4),\ + },{\ + .driver = "kvm64" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(5),\ + },{\ + .driver = "pentium3" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(2),\ + },{\ + .driver = "n270" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(5),\ + },{\ + .driver = "Conroe" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(4),\ + },{\ + .driver = "Penryn" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(4),\ + },{\ + .driver = "Nehalem" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(4),\ + },{\ + .driver = "n270" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Penryn" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Conroe" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Nehalem" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Westmere" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "SandyBridge" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Haswell" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Haswell-noTSX" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Broadwell" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + }, #define HW_COMPAT_2_2 \ /* empty */ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index b4f9461..dfae721 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -695,7 +695,7 @@ struct X86CPUDefinition { static X86CPUDefinition builtin_x86_defs[] = { { .name = "qemu64", - .level = 4, + .level = 0xd, .vendor = CPUID_VENDOR_AMD, .family = 6, .model = 6, @@ -771,7 +771,7 @@ static X86CPUDefinition builtin_x86_defs[] = { }, { .name = "kvm64", - .level = 5, + .level = 0xd, .vendor = CPUID_VENDOR_INTEL, .family = 15, .model = 6, @@ -882,7 +882,7 @@ static X86CPUDefinition builtin_x86_defs[] = { }, { .name = "pentium3", - .level = 2, + .level = 3, .vendor = CPUID_VENDOR_INTEL, .family = 6, .model = 7, @@ -907,8 +907,7 @@ static X86CPUDefinition builtin_x86_defs[] = { }, { .name = "n270", - /* original is on level 10 */ - .level = 5, + .level = 10, .vendor = CPUID_VENDOR_INTEL, .family = 6, .model = 28, @@ -928,12 +927,12 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", }, { .name = "Conroe", - .level = 4, + .level = 10, .vendor = CPUID_VENDOR_INTEL, .family = 6, .model = 15, @@ -950,12 +949,12 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", }, { .name = "Penryn", - .level = 4, + .level = 10, .vendor = CPUID_VENDOR_INTEL, .family = 6, .model = 23, @@ -973,12 +972,12 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", }, { .name = "Nehalem", - .level = 4, + .level = 11, .vendor = CPUID_VENDOR_INTEL, .family = 6, .model = 26, @@ -996,7 +995,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", }, { @@ -1022,7 +1021,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", }, { @@ -1053,7 +1052,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Xeon E312xx (Sandy Bridge)", }, { @@ -1087,7 +1086,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", }, { @@ -1123,7 +1122,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core Processor (Haswell, no TSX)", }, { .name = "Haswell", @@ -1159,7 +1158,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core Processor (Haswell)", }, { @@ -1197,7 +1196,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core Processor (Broadwell, no TSX)", }, { @@ -1235,7 +1234,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core Processor (Broadwell)", }, { -- 2.1.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 2015-07-03 20:47 [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 Eduardo Habkost ` (2 preceding siblings ...) 2015-07-03 20:47 ` [Qemu-devel] [PULL 3/3] target-i386: emulate CPUID level of real hardware Eduardo Habkost @ 2015-07-03 20:52 ` Andreas Färber 2015-07-05 18:33 ` Peter Maydell 4 siblings, 0 replies; 10+ messages in thread From: Andreas Färber @ 2015-07-03 20:52 UTC (permalink / raw) To: Eduardo Habkost, qemu-devel, Peter Maydell Cc: Paolo Bonzini, Richard Henderson Am 03.07.2015 um 22:47 schrieb Eduardo Habkost: > ---------------------------------------------------------------- > X86 queue, 2015-07-03 > > ---------------------------------------------------------------- > > Jan Kiszka (1): > i386: Introduce ARAT CPU feature > > Paolo Bonzini (1): > target-i386: avoid overflow in the tsc-frequency property > > Radim Krčmář (1): > target-i386: emulate CPUID level of real hardware > > include/hw/compat.h | 70 +++++++++++++++++++++++++++++++++++++++++++++++++++- > include/hw/i386/pc.h | 7 +++++- > target-i386/cpu.c | 70 +++++++++++++++++++++++++++++++++++++--------------- > target-i386/cpu.h | 5 +++- > target-i386/kvm.c | 2 ++ > 5 files changed, 131 insertions(+), 23 deletions(-) Ack, :) Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB 21284 (AG Nürnberg) ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 2015-07-03 20:47 [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 Eduardo Habkost ` (3 preceding siblings ...) 2015-07-03 20:52 ` [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 Andreas Färber @ 2015-07-05 18:33 ` Peter Maydell 2015-07-06 13:39 ` Eduardo Habkost 4 siblings, 1 reply; 10+ messages in thread From: Peter Maydell @ 2015-07-05 18:33 UTC (permalink / raw) To: Eduardo Habkost Cc: Paolo Bonzini, Richard Henderson, QEMU Developers, Andreas Färber On 3 July 2015 at 21:47, Eduardo Habkost <ehabkost@redhat.com> wrote: > The following changes since commit 35360642d043c2a5366e8a04a10e5545e7353bd5: > > Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-20150703-1' into staging (2015-07-03 12:05:31 +0100) > > are available in the git repository at: > > git://github.com/ehabkost/qemu.git tags/x86-pull-request > > for you to fetch changes up to de9a6f1c8ab4fcfd9927da5ae28e75efe10f721c: > > target-i386: emulate CPUID level of real hardware (2015-07-03 17:38:25 -0300) > > ---------------------------------------------------------------- > X86 queue, 2015-07-03 Hi. I'm afraid this fails to build: /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c: In function ‘spapr_machine_2_1_class_init’: /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c:1888:34: error: expected ‘}’ before ‘TYPE_X86_CPU’ SPAPR_COMPAT_2_1 ^ /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c:1888:109: error: expected ‘}’ before ‘TYPE_X86_CPU’ SPAPR_COMPAT_2_1 ^ /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c:1888:187: error: expected ‘}’ before ‘TYPE_X86_CPU’ SPAPR_COMPAT_2_1 ^ /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c:1888:261: error: expected ‘}’ before ‘TYPE_X86_CPU’ SPAPR_COMPAT_2_1 ^ /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c:1888:337: error: expected ‘}’ before ‘TYPE_X86_CPU’ SPAPR_COMPAT_2_1 [and further errors, probably just cascade] -- PMM ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 2015-07-05 18:33 ` Peter Maydell @ 2015-07-06 13:39 ` Eduardo Habkost 2015-07-09 18:58 ` Radim Krčmář 2015-07-09 19:07 ` [Qemu-devel] [PATCH build-fix] target-i386: emulate CPUID level of real hardware Radim Krčmář 0 siblings, 2 replies; 10+ messages in thread From: Eduardo Habkost @ 2015-07-06 13:39 UTC (permalink / raw) To: Peter Maydell Cc: Paolo Bonzini, Richard Henderson, QEMU Developers, Andreas Färber On Sun, Jul 05, 2015 at 07:33:31PM +0100, Peter Maydell wrote: > On 3 July 2015 at 21:47, Eduardo Habkost <ehabkost@redhat.com> wrote: > > The following changes since commit 35360642d043c2a5366e8a04a10e5545e7353bd5: > > > > Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-20150703-1' into staging (2015-07-03 12:05:31 +0100) > > > > are available in the git repository at: > > > > git://github.com/ehabkost/qemu.git tags/x86-pull-request > > > > for you to fetch changes up to de9a6f1c8ab4fcfd9927da5ae28e75efe10f721c: > > > > target-i386: emulate CPUID level of real hardware (2015-07-03 17:38:25 -0300) > > > > ---------------------------------------------------------------- > > X86 queue, 2015-07-03 > > Hi. I'm afraid this fails to build: Oops, sorry! I was sure my configure line included non-x86 targets. I will temporarily remove the offending patch and resubmit. > > /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c: In function > ‘spapr_machine_2_1_class_init’: > /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c:1888:34: error: > expected ‘}’ before ‘TYPE_X86_CPU’ > SPAPR_COMPAT_2_1 > ^ > /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c:1888:109: error: > expected ‘}’ before ‘TYPE_X86_CPU’ > SPAPR_COMPAT_2_1 > > ^ > /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c:1888:187: error: > expected ‘}’ before ‘TYPE_X86_CPU’ > SPAPR_COMPAT_2_1 > > ^ > /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c:1888:261: error: > expected ‘}’ before ‘TYPE_X86_CPU’ > SPAPR_COMPAT_2_1 > > ^ > /home/petmay01/linaro/qemu-for-merges/hw/ppc/spapr.c:1888:337: error: > expected ‘}’ before ‘TYPE_X86_CPU’ > SPAPR_COMPAT_2_1 > > [and further errors, probably just cascade] > > -- PMM -- Eduardo ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 2015-07-06 13:39 ` Eduardo Habkost @ 2015-07-09 18:58 ` Radim Krčmář 2015-07-09 19:07 ` [Qemu-devel] [PATCH build-fix] target-i386: emulate CPUID level of real hardware Radim Krčmář 1 sibling, 0 replies; 10+ messages in thread From: Radim Krčmář @ 2015-07-09 18:58 UTC (permalink / raw) To: Eduardo Habkost Cc: Peter Maydell, Richard Henderson, QEMU Developers, Andreas Färber, Paolo Bonzini 2015-07-06 10:39-0300, Eduardo Habkost: > On Sun, Jul 05, 2015 at 07:33:31PM +0100, Peter Maydell wrote: > > On 3 July 2015 at 21:47, Eduardo Habkost <ehabkost@redhat.com> wrote: > > > The following changes since commit 35360642d043c2a5366e8a04a10e5545e7353bd5: > > > > > > Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-20150703-1' into staging (2015-07-03 12:05:31 +0100) > > > > > > are available in the git repository at: > > > > > > git://github.com/ehabkost/qemu.git tags/x86-pull-request > > > > > > for you to fetch changes up to de9a6f1c8ab4fcfd9927da5ae28e75efe10f721c: > > > > > > target-i386: emulate CPUID level of real hardware (2015-07-03 17:38:25 -0300) > > > > > > ---------------------------------------------------------------- > > > X86 queue, 2015-07-03 > > > > Hi. I'm afraid this fails to build: > > Oops, sorry! I was sure my configure line included non-x86 targets. > I will temporarily remove the offending patch and resubmit. My bad, sorry, I will send amended patch shortly. ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH build-fix] target-i386: emulate CPUID level of real hardware 2015-07-06 13:39 ` Eduardo Habkost 2015-07-09 18:58 ` Radim Krčmář @ 2015-07-09 19:07 ` Radim Krčmář 2015-07-15 20:12 ` Eduardo Habkost 1 sibling, 1 reply; 10+ messages in thread From: Radim Krčmář @ 2015-07-09 19:07 UTC (permalink / raw) To: Eduardo Habkost Cc: Peter Maydell, Richard Henderson, QEMU Developers, Andreas Färber, Paolo Bonzini W10 insider has a bug where it ignores CPUID level and interprets CPUID.(EAX=07H, ECX=0H) incorrectly, because CPUID in fact returned CPUID.(EAX=04H, ECX=0H); this resulted in execution of unsupported instructions. While it's a Windows bug, there is no reason to emulate incorrect level. I used http://instlatx64.atw.hu/ as a source of CPUID and checked that it matches Penryn Xeon X5472, Westmere Xeon W3520, SandyBridge i5-2540M, and Haswell i5-4670T. kvm64 and qemu64 were bumped to 0xD to allow all available features for them (and to avoid the same Windows bug). Signed-off-by: Radim Krčmář <rkrcmar@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- build-fix: Moved the definition under PC_COMPAT_2_3. (HW_COMPAT_2_3 isn't there to make the code readable :/) I'll need to search for a HEAD that manages to build, but there shouldn't be any more problems with this patch now. include/hw/i386/pc.h | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++++ target-i386/cpu.c | 37 ++++++++++++++-------------- 2 files changed, 86 insertions(+), 19 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 15e335296719..c4165740cf1c 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -298,6 +298,74 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = TYPE_X86_CPU,\ .property = "arat",\ .value = "off",\ + },{\ + .driver = "qemu64" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(4),\ + },{\ + .driver = "kvm64" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(5),\ + },{\ + .driver = "pentium3" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(2),\ + },{\ + .driver = "n270" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(5),\ + },{\ + .driver = "Conroe" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(4),\ + },{\ + .driver = "Penryn" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(4),\ + },{\ + .driver = "Nehalem" "-" TYPE_X86_CPU,\ + .property = "level",\ + .value = stringify(4),\ + },{\ + .driver = "n270" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Penryn" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Conroe" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Nehalem" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Westmere" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "SandyBridge" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Haswell" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Haswell-noTSX" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Broadwell" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ + },{\ + .driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,\ + .property = "xlevel",\ + .value = stringify(0x8000000a),\ }, #define PC_COMPAT_2_2 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index f9b1788cbda2..3b88ba600808 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -695,7 +695,7 @@ struct X86CPUDefinition { static X86CPUDefinition builtin_x86_defs[] = { { .name = "qemu64", - .level = 4, + .level = 0xd, .vendor = CPUID_VENDOR_AMD, .family = 6, .model = 6, @@ -771,7 +771,7 @@ static X86CPUDefinition builtin_x86_defs[] = { }, { .name = "kvm64", - .level = 5, + .level = 0xd, .vendor = CPUID_VENDOR_INTEL, .family = 15, .model = 6, @@ -882,7 +882,7 @@ static X86CPUDefinition builtin_x86_defs[] = { }, { .name = "pentium3", - .level = 2, + .level = 3, .vendor = CPUID_VENDOR_INTEL, .family = 6, .model = 7, @@ -907,8 +907,7 @@ static X86CPUDefinition builtin_x86_defs[] = { }, { .name = "n270", - /* original is on level 10 */ - .level = 5, + .level = 10, .vendor = CPUID_VENDOR_INTEL, .family = 6, .model = 28, @@ -928,12 +927,12 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", }, { .name = "Conroe", - .level = 4, + .level = 10, .vendor = CPUID_VENDOR_INTEL, .family = 6, .model = 15, @@ -950,12 +949,12 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", }, { .name = "Penryn", - .level = 4, + .level = 10, .vendor = CPUID_VENDOR_INTEL, .family = 6, .model = 23, @@ -973,12 +972,12 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", }, { .name = "Nehalem", - .level = 4, + .level = 11, .vendor = CPUID_VENDOR_INTEL, .family = 6, .model = 26, @@ -996,7 +995,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", }, { @@ -1022,7 +1021,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", }, { @@ -1053,7 +1052,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Xeon E312xx (Sandy Bridge)", }, { @@ -1087,7 +1086,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", }, { @@ -1123,7 +1122,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core Processor (Haswell, no TSX)", }, { .name = "Haswell", @@ -1159,7 +1158,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core Processor (Haswell)", }, { @@ -1197,7 +1196,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core Processor (Broadwell, no TSX)", }, { @@ -1235,7 +1234,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT, - .xlevel = 0x8000000A, + .xlevel = 0x80000008, .model_id = "Intel Core Processor (Broadwell)", }, { -- 2.4.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH build-fix] target-i386: emulate CPUID level of real hardware 2015-07-09 19:07 ` [Qemu-devel] [PATCH build-fix] target-i386: emulate CPUID level of real hardware Radim Krčmář @ 2015-07-15 20:12 ` Eduardo Habkost 0 siblings, 0 replies; 10+ messages in thread From: Eduardo Habkost @ 2015-07-15 20:12 UTC (permalink / raw) To: Radim Krčmář Cc: Peter Maydell, Paolo Bonzini, QEMU Developers, Andreas Färber, Richard Henderson On Thu, Jul 09, 2015 at 09:07:39PM +0200, Radim Krčmář wrote: > W10 insider has a bug where it ignores CPUID level and interprets > CPUID.(EAX=07H, ECX=0H) incorrectly, because CPUID in fact returned > CPUID.(EAX=04H, ECX=0H); this resulted in execution of unsupported > instructions. > > While it's a Windows bug, there is no reason to emulate incorrect level. > > I used http://instlatx64.atw.hu/ as a source of CPUID and checked that > it matches Penryn Xeon X5472, Westmere Xeon W3520, SandyBridge i5-2540M, > and Haswell i5-4670T. > > kvm64 and qemu64 were bumped to 0xD to allow all available features for > them (and to avoid the same Windows bug). > > Signed-off-by: Radim Krčmář <rkrcmar@redhat.com> > Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Thanks, applied to x86 tree. As the existing code prevents a guest OS from running, I consider it a bug fix. -- Eduardo ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2015-07-15 20:12 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-07-03 20:47 [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 Eduardo Habkost 2015-07-03 20:47 ` [Qemu-devel] [PULL 1/3] i386: Introduce ARAT CPU feature Eduardo Habkost 2015-07-03 20:47 ` [Qemu-devel] [PULL 2/3] target-i386: avoid overflow in the tsc-frequency property Eduardo Habkost 2015-07-03 20:47 ` [Qemu-devel] [PULL 3/3] target-i386: emulate CPUID level of real hardware Eduardo Habkost 2015-07-03 20:52 ` [Qemu-devel] [PULL 0/3] X86 queue, 2015-07-03 Andreas Färber 2015-07-05 18:33 ` Peter Maydell 2015-07-06 13:39 ` Eduardo Habkost 2015-07-09 18:58 ` Radim Krčmář 2015-07-09 19:07 ` [Qemu-devel] [PATCH build-fix] target-i386: emulate CPUID level of real hardware Radim Krčmář 2015-07-15 20:12 ` Eduardo Habkost
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