From: Aurelien Jarno <aurelien@aurel32.net>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: claudio.fontana@huawei.com, qemu-devel@nongnu.org, rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH 1/2] tcg: aarch64: add ext argument to tcg_out_insn_3310
Date: Wed, 15 Jul 2015 18:09:51 +0200 [thread overview]
Message-ID: <20150715160951.GC472@aurel32.net> (raw)
In-Reply-To: <1436974021-28978-2-git-send-email-pbonzini@redhat.com>
On 2015-07-15 17:27, Paolo Bonzini wrote:
> The new argument lets you pick uxtw or uxtx mode for the offset
> register. For now, all callers pass TCG_TYPE_I64 so that uxtx
> is generated. The bits for uxtx are removed from I3312_TO_I3310.
>
> Reported-by: Leon Alrae <leon.alrae@imgtec.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> tcg/aarch64/tcg-target.c | 41 ++++++++++++++++++++++-------------------
> 1 file changed, 22 insertions(+), 19 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
> index fe44ad7..5395202 100644
> --- a/tcg/aarch64/tcg-target.c
> +++ b/tcg/aarch64/tcg-target.c
> @@ -280,7 +280,7 @@ typedef enum {
> I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,
> I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,
>
> - I3312_TO_I3310 = 0x00206800,
> + I3312_TO_I3310 = 0x00200800,
> I3312_TO_I3313 = 0x01000000,
>
> /* Load/store register pair instructions. */
> @@ -496,13 +496,14 @@ static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext,
> }
>
> static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,
> - TCGReg rd, TCGReg base, TCGReg regoff)
> + TCGReg rd, TCGReg base, TCGType ext,
> + TCGReg regoff)
> {
> /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
> - tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 | base << 5 | rd);
> + tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 |
> + 0x4000 | ext << 13 | base << 5 | rd);
> }
>
> -
> static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn,
> TCGReg rd, TCGReg rn, intptr_t offset)
> {
> @@ -677,7 +678,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn,
>
> /* Worst-case scenario, move offset to temp register, use reg offset. */
> tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset);
> - tcg_out_ldst_r(s, insn, rd, rn, TCG_REG_TMP);
> + tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP);
> }
>
> static inline void tcg_out_mov(TCGContext *s,
> @@ -1111,48 +1112,49 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,
> TCGReg data_r, TCGReg addr_r, TCGReg off_r)
> {
> const TCGMemOp bswap = memop & MO_BSWAP;
> + const TCGType otype = TCG_TYPE_I64;
>
> switch (memop & MO_SSIZE) {
> case MO_UB:
> - tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r);
> break;
> case MO_SB:
> tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW,
> - data_r, addr_r, off_r);
> + data_r, addr_r, otype, off_r);
> break;
> case MO_UW:
> - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
> if (bswap) {
> tcg_out_rev16(s, data_r, data_r);
> }
> break;
> case MO_SW:
> if (bswap) {
> - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
> tcg_out_rev16(s, data_r, data_r);
> tcg_out_sxt(s, ext, MO_16, data_r, data_r);
> } else {
> - tcg_out_ldst_r(s, ext ? I3312_LDRSHX : I3312_LDRSHW,
> - data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
> + data_r, addr_r, otype, off_r);
> }
> break;
> case MO_UL:
> - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
> if (bswap) {
> tcg_out_rev32(s, data_r, data_r);
> }
> break;
> case MO_SL:
> if (bswap) {
> - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
> tcg_out_rev32(s, data_r, data_r);
> tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r);
> } else {
> - tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);
> }
> break;
> case MO_Q:
> - tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);
> if (bswap) {
> tcg_out_rev64(s, data_r, data_r);
> }
> @@ -1166,31 +1168,32 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,
> TCGReg data_r, TCGReg addr_r, TCGReg off_r)
> {
> const TCGMemOp bswap = memop & MO_BSWAP;
> + const TCGType otype = TCG_TYPE_I64;
>
> switch (memop & MO_SIZE) {
> case MO_8:
> - tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);
> break;
> case MO_16:
> if (bswap && data_r != TCG_REG_XZR) {
> tcg_out_rev16(s, TCG_REG_TMP, data_r);
> data_r = TCG_REG_TMP;
> }
> - tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);
> break;
> case MO_32:
> if (bswap && data_r != TCG_REG_XZR) {
> tcg_out_rev32(s, TCG_REG_TMP, data_r);
> data_r = TCG_REG_TMP;
> }
> - tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);
> break;
> case MO_64:
> if (bswap && data_r != TCG_REG_XZR) {
> tcg_out_rev64(s, TCG_REG_TMP, data_r);
> data_r = TCG_REG_TMP;
> }
> - tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, off_r);
> + tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r);
> break;
> default:
> tcg_abort();
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2015-07-15 16:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-15 15:26 [Qemu-devel] [PATCH 0/2] tcg: aarch64: use 32-bit offset for 32-bit user-mode emulation Paolo Bonzini
2015-07-15 15:27 ` [Qemu-devel] [PATCH 1/2] tcg: aarch64: add ext argument to tcg_out_insn_3310 Paolo Bonzini
2015-07-15 16:09 ` Aurelien Jarno [this message]
2015-07-15 15:27 ` [Qemu-devel] [PATCH 2/2] tcg: aarch64: use 32-bit offset for 32-bit user-mode emulation Paolo Bonzini
2015-07-15 16:10 ` Aurelien Jarno
2015-07-23 21:19 ` [Qemu-devel] [PATCH 0/2] " Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150715160951.GC472@aurel32.net \
--to=aurelien@aurel32.net \
--cc=claudio.fontana@huawei.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=rth@twiddle.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).