From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40895) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZG2o6-0003Oh-UM for qemu-devel@nongnu.org; Fri, 17 Jul 2015 06:23:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZG2o6-0000U2-3Q for qemu-devel@nongnu.org; Fri, 17 Jul 2015 06:23:54 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:33773) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZG2o5-0000Sy-Tb for qemu-devel@nongnu.org; Fri, 17 Jul 2015 06:23:54 -0400 Date: Fri, 17 Jul 2015 12:23:50 +0200 From: Aurelien Jarno Message-ID: <20150717102350.GA15281@aurel32.net> References: <20150715205423.GA23115@aurel32.net> <55A82251.6020308@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <55A82251.6020308@twiddle.net> Subject: Re: [Qemu-devel] [PATCH v2 00/13] tcg/sparc v8plus code generation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Paolo Bonzini , qemu-devel@nongnu.org On 2015-07-16 22:29, Richard Henderson wrote: > On 07/15/2015 09:54 PM, Aurelien Jarno wrote: > >While I understand why we need the new trunc_shr_i32 opcode for MIPS64 > >(the 32-bit values must be kept sign-extended), I currently fail to > >see why it is needed for SPARC. > > As far as I recall, it improves code for extracting high parts of 64-bit > quantities. Without this, we wind up with a 64-bit shift, requiring a > 64-bit temp register, followed by the "real" truncate which can copy the > data to a 32-bit destination register. Ok, I understand the use case now. So it's not for correctness, but rather to generate more optimized code. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net