From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56880) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZHZTz-0006uJ-5R for qemu-devel@nongnu.org; Tue, 21 Jul 2015 11:29:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZHZTx-0003dW-PB for qemu-devel@nongnu.org; Tue, 21 Jul 2015 11:29:27 -0400 Date: Tue, 21 Jul 2015 17:29:12 +0200 From: Aurelien Jarno Message-ID: <20150721152912.GA30591@aurel32.net> References: <1437455978.5809.2.camel@kernel.crashing.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1437455978.5809.2.camel@kernel.crashing.org> Subject: Re: [Qemu-devel] [PATCH v3] tcg/ppc: Improve unaligned load/store handling on 64-bit backend List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: Alexander Graf , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Richard Henderson On 2015-07-21 15:19, Benjamin Herrenschmidt wrote: > Currently, we get to the slow path for any unaligned access in the > backend, because we effectively preserve the bottom address bits > below the alignment requirement when comparing with the TLB entry, > so any non-0 bit there will cause the compare to fail. > > For the same number of instructions, we can instead add the access > size - 1 to the address and stick to clearing all the bottom bits. > > That means that normal unaligned accesses will not fallback (the HW > will handle them fine). Only when crossing a page boundary well we > end up having a mismatch because we'll end up pointing to the next > page which cannot possibly be in that same TLB entry. > > Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net