From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55693) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZHqN7-0000BG-Ux for qemu-devel@nongnu.org; Wed, 22 Jul 2015 05:31:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZHqN3-0008SX-Co for qemu-devel@nongnu.org; Wed, 22 Jul 2015 05:31:29 -0400 Received: from mail-wi0-x22a.google.com ([2a00:1450:400c:c05::22a]:35406) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZHqN3-0008SH-5n for qemu-devel@nongnu.org; Wed, 22 Jul 2015 05:31:25 -0400 Received: by wibxm9 with SMTP id xm9so154571594wib.0 for ; Wed, 22 Jul 2015 02:31:24 -0700 (PDT) Date: Wed, 22 Jul 2015 10:31:20 +0100 From: Stefan Hajnoczi Message-ID: <20150722093120.GC2905@stefanha-thinkpad.redhat.com> References: <1437494626-3773-1-git-send-email-markmb@redhat.com> <1437494626-3773-3-git-send-email-markmb@redhat.com> <20150722042434.GB27877@morn.localdomain> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="jousvV0MzM2p6OtC" Content-Disposition: inline In-Reply-To: <20150722042434.GB27877@morn.localdomain> Subject: Re: [Qemu-devel] [RFC 2/7] fw_cfg dma interface List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Kevin O'Connor Cc: Paolo Bonzini , Marc =?iso-8859-1?Q?Mar=ED?= , qemu-devel@nongnu.org, Gerd Hoffmann --jousvV0MzM2p6OtC Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jul 22, 2015 at 12:24:34AM -0400, Kevin O'Connor wrote: > On Tue, Jul 21, 2015 at 06:03:41PM +0200, Marc Mar=ED wrote: > > From: Gerd Hoffmann > >=20 > > First draft of a fw_cfg dma interface. Designed as add-on to the > > extisting fw_cfg interface, i.e. there is no select register. There > > are four 32bit registers: Target address (low and high bits), transfer > > length, control register. >=20 > If I read this interface correctly, a guest will have at least six > faults to complete a typical fw_cfg dma transfer (select, target low, > target high, transfer length, control register write, control register > read). I wonder if using a DMA transfer descriptor might be more > efficient. >=20 > That is, if a transfer descriptor was defined with something like: >=20 > struct fwcfg_dma { > u16 command; > u16 select; > u32 transfer_length; > u64 target_addr; > } PACKED; >=20 > and QEMU was informed of the transfer descriptor address (one fault on > 32bit addresses; two faults on 64bit addresses) then QEMU could read > the transfer descriptor, perform the requested operation, and then > update the transfer descriptor on completion. This would reduce the > total number of faults between QEMU and the firmware, and allow for a > more flexible interface for future growth. I like the idea. In Marc's case of benchmarking -kernel/-initrd times it may not make a big difference, but if we're going to add a new interface it might as well be optimal. --jousvV0MzM2p6OtC Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAEBAgAGBQJVr2LoAAoJEJykq7OBq3PI7vAIAMqtqUar2ObYpvtdacjSNsUq 3BBG5BD5xcq0CFwz7zr3m0fKbt9Wlo9MbvAGW5eZhOPtSO4xo3ZB+BKvDxCqV96e fVsyK0QxcZU9cZeJ4luHrfck33Lx3ftgBqCszdGdwZvcCF2bVnJwpYhYCR2S25Nq g7X1sdOU82F8REiIqjhm7hgV5D4pcBfPudh3v8a7fm+gLKgpzUOxic3KESJcyOw+ toW+ThS7SjuUQaYgbcsQrDvZdYlPepPpA249APG/hO4ux5B7HBGkoLsa2f3lKUlP 02lebzpPe62Y1S/fwK5vHL/eQylAe02l19Ofuk3lE2SWQj0wV9vXz+mPVInSSr8= =Fjog -----END PGP SIGNATURE----- --jousvV0MzM2p6OtC--