Re: [Qemu-devel] [Qemu-ppc] [PATCH v2] pci: allow 0 address for PCI IO/MEM regions

["Michael S. Tsirkin" <mst@redhat.com>]

On Thu, Jul 23, 2015 at 10:00:30PM +0100, Peter Maydell wrote:
> On 23 July 2015 at 21:46, Benjamin Herrenschmidt
> <benh@kernel.crashing.org> wrote:
> > On Thu, 2015-07-23 at 20:24 +0200, Laurent Vivier wrote:
> >> From: Michael Roth <mdroth@linux.vnet.ibm.com>
> >>
> >> Some kernels program a 0 address for io regions. PCI 3.0 spec
> >> section 6.2.5.1 doesn't seem to disallow this.
> >>
> >> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
> >> [lvivier: add pci_allow_0_addr in MachineClass to conditionally
> >> allow addr 0 for pseries, as this can break other architectures]
> >> Signed-off-by: Laurent Vivier <lvivier@redhat.com>
> >> ---
> >
> > Why would it break other architectures ? The PCI bus will forward
> > address 0 just fine and some devices will decode it just fine too,
> > regardless of the architecture they are put on. I don't see why
> > having BARs capable of decoding it would break anything...
> 
> Discussion from last time around:
> http://lists.gnu.org/archive/html/qemu-devel/2015-01/msg01358.html
> 
> suggests that it's a workaround for our PC model being buggy
> and putting 0-address BARs over the top of some other system
> device rather than underneath them...
> 
> (Also, none of our PCI device models actually try to do
> the "BAR at zero means I won't respond" behaviour, which
> presumably they might do in real life.)
> 
> -- PMM

Maybe some devices do this, but I'm guessing not all of them,
since there's no hint in the pci spec that they should.

-- 
MST