From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45564) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZLF9i-0006jn-Rk for qemu-devel@nongnu.org; Fri, 31 Jul 2015 14:35:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZLF9b-0001i8-OP for qemu-devel@nongnu.org; Fri, 31 Jul 2015 14:35:42 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55211) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZLF9b-0001ho-Js for qemu-devel@nongnu.org; Fri, 31 Jul 2015 14:35:35 -0400 Date: Fri, 31 Jul 2015 20:35:29 +0200 From: Andrew Jones Message-ID: <20150731183529.GF3680@hawk.localdomain> References: <1438358041-18021-1-git-send-email-alex.bennee@linaro.org> <1438358041-18021-7-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <1438358041-18021-7-git-send-email-alex.bennee@linaro.org> Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [kvm-unit-tests PATCH v5 06/11] lib/arm: add flush_tlb_page mmu function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?iso-8859-1?Q?Benn=E9e?= Cc: mttcg@greensocs.com, peter.maydell@linaro.org, claudio.fontana@huawei.com, kvm@vger.kernel.org, a.spyridakis@virtualopensystems.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com On Fri, Jul 31, 2015 at 04:53:56PM +0100, Alex Benn=E9e wrote: > This introduces a new flush_tlb_page function which does exactly what > you expect. It's going to be useful for the future TLB torture test. >=20 > Signed-off-by: Alex Benn=E9e > --- > lib/arm/asm/mmu.h | 11 +++++++++++ > lib/arm64/asm/mmu.h | 8 ++++++++ > 2 files changed, 19 insertions(+) >=20 > diff --git a/lib/arm/asm/mmu.h b/lib/arm/asm/mmu.h > index c1bd01c..2bb0cde 100644 > --- a/lib/arm/asm/mmu.h > +++ b/lib/arm/asm/mmu.h > @@ -14,8 +14,11 @@ > #define PTE_AF PTE_EXT_AF > #define PTE_WBWA L_PTE_MT_WRITEALLOC > =20 > +/* See B3.18.7 TLB maintenance operations */ > + > static inline void local_flush_tlb_all(void) > { > + /* TLBIALL */ > asm volatile("mcr p15, 0, %0, c8, c7, 0" :: "r" (0)); > dsb(); > isb(); > @@ -27,6 +30,14 @@ static inline void flush_tlb_all(void) > local_flush_tlb_all(); > } > =20 > +static inline void flush_tlb_page(unsigned long vaddr) > +{ > + /* TLBIMVAA */ > + asm volatile("mcr p15, 0, %0, c8, c7, 3" :: "r" (vaddr)); > + dsb(); > + isb(); > +} > + > #include > =20 > #endif /* __ASMARM_MMU_H_ */ > diff --git a/lib/arm64/asm/mmu.h b/lib/arm64/asm/mmu.h > index 18b4d6b..3bc31c9 100644 > --- a/lib/arm64/asm/mmu.h > +++ b/lib/arm64/asm/mmu.h > @@ -19,6 +19,14 @@ static inline void flush_tlb_all(void) > isb(); > } > =20 > +static inline void flush_tlb_page(unsigned long vaddr) > +{ > + unsigned long page =3D vaddr >> 12; > + dsb(ishst); > + asm("tlbi vaae1is, %0" :: "r" (page)); > + dsb(ish); > +} > + > #include > =20 > #endif /* __ASMARM64_MMU_H_ */ > --=20 > 2.5.0 >=20 > Reviewed-by: Andrew Jones =20