From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:49567)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <edgar.iglesias@gmail.com>) id 1ZQJ08-0000AP-4H
	for qemu-devel@nongnu.org; Fri, 14 Aug 2015 13:42:44 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <edgar.iglesias@gmail.com>) id 1ZQJ04-0001ft-Te
	for qemu-devel@nongnu.org; Fri, 14 Aug 2015 13:42:44 -0400
Received: from mail-la0-x22b.google.com ([2a00:1450:4010:c03::22b]:36213)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <edgar.iglesias@gmail.com>) id 1ZQJ04-0001ex-LR
	for qemu-devel@nongnu.org; Fri, 14 Aug 2015 13:42:40 -0400
Received: by lagz9 with SMTP id z9so47870727lag.3
	for <qemu-devel@nongnu.org>; Fri, 14 Aug 2015 10:42:39 -0700 (PDT)
Date: Fri, 14 Aug 2015 19:42:37 +0200
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Message-ID: <20150814174237.GC27827@toto>
References: <1438281398-18746-1-git-send-email-peter.maydell@linaro.org>
	<CAFEAcA8UG1mtyK3jVAju6Z+k4Jb6-zE54gGAKG_xF-00c8rS7w@mail.gmail.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <CAFEAcA8UG1mtyK3jVAju6Z+k4Jb6-zE54gGAKG_xF-00c8rS7w@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH 0/4] target-arm: Implement missing EL3 (and
 EL2) registers
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>, Patch Tracking <patches@linaro.org>

On Fri, Aug 14, 2015 at 11:12:55AM +0100, Peter Maydell wrote:
> Ping?
> 

Hi! Sorry for the delay! I'll have a look at this over the weekend.
Do you happen to have the patches all applied in a branch somewhere?

Thanks,
Edgar


> thanks
> -- PMM
> 
> On 30 July 2015 at 19:36, Peter Maydell <peter.maydell@linaro.org> wrote:
> > This series adds a handful of EL3 system registers that
> > we were missing. It also includes the EL2 flavours
> > where there were obvious easy parallels. I think this
> > means we now have all the EL3 sysregs we care about.
> > (A previous series added missing address translation
> > operations; I still have to do the missing TLB ops.)
> >
> > None of these registers are exciting; they're all either
> > reads-as-written or RAZ/WI.
> >
> > A note for people who care about EL2: I notice that a
> > lot of AArch32 EL2 registers have the access permission
> > pattern of "accessible from EL2(NS) and from EL3 if
> > SCR.NS==1, but traps if accessed from EL3 if SCR.NS==0".
> > We don't implement this wrinkle (we won't trap the
> > erroneous EL3 access). This is true of the EL2 regs I
> > add here, but then it's true of all our existing ones...
> >
> > Peter Maydell (4):
> >   target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
> >   target-arm: Implement missing AMAIR registers
> >   target-arm: Implement missing AFSR registers
> >   target-arm: Implement missing ACTLR registers
> >
> >  target-arm/helper.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++-----
> >  1 file changed, 68 insertions(+), 6 deletions(-)
> >