From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41837) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZR5sX-0003aV-8j for qemu-devel@nongnu.org; Sun, 16 Aug 2015 17:54:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZR5sU-0008Tc-2F for qemu-devel@nongnu.org; Sun, 16 Aug 2015 17:54:09 -0400 Received: from mail-pd0-x235.google.com ([2607:f8b0:400e:c02::235]:36443) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZR5sT-0008TM-RH for qemu-devel@nongnu.org; Sun, 16 Aug 2015 17:54:06 -0400 Received: by pdbmi9 with SMTP id mi9so7992705pdb.3 for ; Sun, 16 Aug 2015 14:54:04 -0700 (PDT) Date: Sun, 16 Aug 2015 23:54:02 +0200 From: "Edgar E. Iglesias" Message-ID: <20150816215402.GA16713@toto> References: <1438281398-18746-1-git-send-email-peter.maydell@linaro.org> <1438281398-18746-2-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1438281398-18746-2-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 1/4] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org On Thu, Jul 30, 2015 at 07:36:35PM +0100, Peter Maydell wrote: > Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only > two which we had implemented the 32-bit Secure equivalents of but > not the 64-bit Secure versions. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/helper.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 01f0d0d..d59616e 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1022,6 +1022,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { > .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, > .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), > .resetvalue = 0 }, > + { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), > + .resetvalue = 0 }, > /* For non-long-descriptor page tables these are PRRR and NMRR; > * regardless they still act as reads-as-written for QEMU. > */ > @@ -2790,6 +2794,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { > .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, > .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, > .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, > + { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, > + .access = PL3_RW, .resetvalue = 0, > + .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, > REGINFO_SENTINEL > }; > > -- > 1.9.1 >