From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43903) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZR63q-0008Sc-OX for qemu-devel@nongnu.org; Sun, 16 Aug 2015 18:05:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZR63l-00087b-VU for qemu-devel@nongnu.org; Sun, 16 Aug 2015 18:05:50 -0400 Received: from mail-pd0-x236.google.com ([2607:f8b0:400e:c02::236]:33430) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZR63l-00087J-OJ for qemu-devel@nongnu.org; Sun, 16 Aug 2015 18:05:45 -0400 Received: by pdrh1 with SMTP id h1so49036605pdr.0 for ; Sun, 16 Aug 2015 15:05:45 -0700 (PDT) Date: Mon, 17 Aug 2015 00:05:43 +0200 From: "Edgar E. Iglesias" Message-ID: <20150816220543.GC16713@toto> References: <1438281398-18746-1-git-send-email-peter.maydell@linaro.org> <1438281398-18746-4-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1438281398-18746-4-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 3/4] target-arm: Implement missing AFSR registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org On Thu, Jul 30, 2015 at 07:36:37PM +0100, Peter Maydell wrote: > The AFSR registers are implementation dependent auxiliary fault > status registers. We already implemented a RAZ/WI AFSR0_EL1 and > AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/helper.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 781b3a2..d286680 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2610,6 +2610,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { > .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, > .access = PL2_RW, .type = ARM_CP_CONST, > .resetvalue = 0 }, > + { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, > + .access = PL2_RW, .type = ARM_CP_CONST, > + .resetvalue = 0 }, > + { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, > + .access = PL2_RW, .type = ARM_CP_CONST, > + .resetvalue = 0 }, > { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, > .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > @@ -2713,6 +2721,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, > .access = PL2_RW, .type = ARM_CP_CONST, > .resetvalue = 0 }, > + { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, > + .access = PL2_RW, .type = ARM_CP_CONST, > + .resetvalue = 0 }, > + { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, > + .access = PL2_RW, .type = ARM_CP_CONST, > + .resetvalue = 0 }, > { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, > .access = PL2_RW, .writefn = vmsa_tcr_el1_write, > @@ -2819,6 +2835,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { > .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, > .access = PL3_RW, .type = ARM_CP_CONST, > .resetvalue = 0 }, > + { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, > + .access = PL3_RW, .type = ARM_CP_CONST, > + .resetvalue = 0 }, > + { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, > + .access = PL3_RW, .type = ARM_CP_CONST, > + .resetvalue = 0 }, > REGINFO_SENTINEL > }; > > -- > 1.9.1 >