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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 4/4] target-arm: Implement missing ACTLR registers
Date: Mon, 17 Aug 2015 00:09:09 +0200	[thread overview]
Message-ID: <20150816220909.GD16713@toto> (raw)
In-Reply-To: <1438281398-18746-5-git-send-email-peter.maydell@linaro.org>

On Thu, Jul 30, 2015 at 07:36:38PM +0100, Peter Maydell wrote:
> We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and
> ACTLR_EL3, for consistency.
> 
> Since we don't currently have any CPUs that need the EL2/EL3
> versions to reset to non-zero values, implement as RAZ/WI.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>


> ---
>  target-arm/helper.c | 21 +++++++++++++++------
>  1 file changed, 15 insertions(+), 6 deletions(-)
> 
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d286680..b0b1a22 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3637,13 +3637,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>      }
>  
>      if (arm_feature(env, ARM_FEATURE_AUXCR)) {
> -        ARMCPRegInfo auxcr = {
> -            .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
> -            .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
> -            .access = PL1_RW, .type = ARM_CP_CONST,
> -            .resetvalue = cpu->reset_auxcr
> +        ARMCPRegInfo auxcr_reginfo[] = {
> +            { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
> +              .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
> +              .access = PL1_RW, .type = ARM_CP_CONST,
> +              .resetvalue = cpu->reset_auxcr },
> +            { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
> +              .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
> +              .access = PL2_RW, .type = ARM_CP_CONST,
> +              .resetvalue = 0 },
> +            { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
> +              .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
> +              .access = PL3_RW, .type = ARM_CP_CONST,
> +              .resetvalue = 0 },
> +            REGINFO_SENTINEL
>          };
> -        define_one_arm_cp_reg(cpu, &auxcr);
> +        define_arm_cp_regs(cpu, auxcr_reginfo);
>      }
>  
>      if (arm_feature(env, ARM_FEATURE_CBAR)) {
> -- 
> 1.9.1
> 

  reply	other threads:[~2015-08-16 22:09 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-30 18:36 [Qemu-devel] [PATCH 0/4] target-arm: Implement missing EL3 (and EL2) registers Peter Maydell
2015-07-30 18:36 ` [Qemu-devel] [PATCH 1/4] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers Peter Maydell
2015-08-16 21:54   ` Edgar E. Iglesias
2015-07-30 18:36 ` [Qemu-devel] [PATCH 2/4] target-arm: Implement missing AMAIR registers Peter Maydell
2015-08-16 22:02   ` Edgar E. Iglesias
2015-07-30 18:36 ` [Qemu-devel] [PATCH 3/4] target-arm: Implement missing AFSR registers Peter Maydell
2015-08-16 22:05   ` Edgar E. Iglesias
2015-07-30 18:36 ` [Qemu-devel] [PATCH 4/4] target-arm: Implement missing ACTLR registers Peter Maydell
2015-08-16 22:09   ` Edgar E. Iglesias [this message]
2015-08-14 10:12 ` [Qemu-devel] [PATCH 0/4] target-arm: Implement missing EL3 (and EL2) registers Peter Maydell
2015-08-14 17:42   ` Edgar E. Iglesias
2015-08-14 17:48     ` Peter Maydell
2015-08-14 17:55       ` Edgar E. Iglesias

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