[Qemu-devel] [PATCH 0/4] target-arm: Implement missing EL3 (and EL2) registers

[Qemu-devel] [PATCH 0/4] target-arm: Implement missing EL3 (and EL2) registers

[Peter Maydell]

This series adds a handful of EL3 system registers that
we were missing. It also includes the EL2 flavours
where there were obvious easy parallels. I think this
means we now have all the EL3 sysregs we care about.
(A previous series added missing address translation
operations; I still have to do the missing TLB ops.)

None of these registers are exciting; they're all either
reads-as-written or RAZ/WI.

A note for people who care about EL2: I notice that a
lot of AArch32 EL2 registers have the access permission
pattern of "accessible from EL2(NS) and from EL3 if
SCR.NS==1, but traps if accessed from EL3 if SCR.NS==0".
We don't implement this wrinkle (we won't trap the
erroneous EL3 access). This is true of the EL2 regs I
add here, but then it's true of all our existing ones...

Peter Maydell (4):
  target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
  target-arm: Implement missing AMAIR registers
  target-arm: Implement missing AFSR registers
  target-arm: Implement missing ACTLR registers

 target-arm/helper.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 68 insertions(+), 6 deletions(-)

-- 
1.9.1

[Qemu-devel] [PATCH 1/4] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers

[Peter Maydell]

Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only
two which we had implemented the 32-bit Secure equivalents of but
not the 64-bit Secure versions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 01f0d0d..d59616e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1022,6 +1022,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
       .resetvalue = 0 },
+    { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
+      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
+      .resetvalue = 0 },
     /* For non-long-descriptor page tables these are PRRR and NMRR;
      * regardless they still act as reads-as-written for QEMU.
      */
@@ -2790,6 +2794,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
+    { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
+      .access = PL3_RW, .resetvalue = 0,
+      .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
     REGINFO_SENTINEL
 };
 
-- 
1.9.1

[Qemu-devel] [PATCH 2/4] target-arm: Implement missing AMAIR registers

[Peter Maydell]

The AMAIR registers are for providing auxiliary implementation
defined memory attributes. We already implemented a RAZ/WI
AMAIR_EL1; add the EL2 and EL3 versions for consistency.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index d59616e..781b3a2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2602,6 +2602,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
+      .access = PL2_RW, .type = ARM_CP_CONST,
+      .resetvalue = 0 },
+    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
+      .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
+      .access = PL2_RW, .type = ARM_CP_CONST,
+      .resetvalue = 0 },
     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2696,6 +2704,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
       .access = PL2_RW, .type = ARM_CP_ALIAS,
       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
+    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
+      .access = PL2_RW, .type = ARM_CP_CONST,
+      .resetvalue = 0 },
+    /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
+    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
+      .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
+      .access = PL2_RW, .type = ARM_CP_CONST,
+      .resetvalue = 0 },
     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
       .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
@@ -2798,6 +2815,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
       .access = PL3_RW, .resetvalue = 0,
       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
+    { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
+      .access = PL3_RW, .type = ARM_CP_CONST,
+      .resetvalue = 0 },
     REGINFO_SENTINEL
 };
 
-- 
1.9.1

[Qemu-devel] [PATCH 3/4] target-arm: Implement missing AFSR registers

[Peter Maydell]

The AFSR registers are implementation dependent auxiliary fault
status registers. We already implemented a RAZ/WI AFSR0_EL1 and
AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 781b3a2..d286680 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2610,6 +2610,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
       .access = PL2_RW, .type = ARM_CP_CONST,
       .resetvalue = 0 },
+    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
+      .access = PL2_RW, .type = ARM_CP_CONST,
+      .resetvalue = 0 },
+    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
+      .access = PL2_RW, .type = ARM_CP_CONST,
+      .resetvalue = 0 },
     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2713,6 +2721,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
       .access = PL2_RW, .type = ARM_CP_CONST,
       .resetvalue = 0 },
+    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
+      .access = PL2_RW, .type = ARM_CP_CONST,
+      .resetvalue = 0 },
+    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
+      .access = PL2_RW, .type = ARM_CP_CONST,
+      .resetvalue = 0 },
     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
       .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
@@ -2819,6 +2835,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
       .access = PL3_RW, .type = ARM_CP_CONST,
       .resetvalue = 0 },
+    { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
+      .access = PL3_RW, .type = ARM_CP_CONST,
+      .resetvalue = 0 },
+    { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
+      .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
+      .access = PL3_RW, .type = ARM_CP_CONST,
+      .resetvalue = 0 },
     REGINFO_SENTINEL
 };
 
-- 
1.9.1

[Qemu-devel] [PATCH 4/4] target-arm: Implement missing ACTLR registers

[Peter Maydell]

We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and
ACTLR_EL3, for consistency.

Since we don't currently have any CPUs that need the EL2/EL3
versions to reset to non-zero values, implement as RAZ/WI.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index d286680..b0b1a22 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3637,13 +3637,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
     }
 
     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
-        ARMCPRegInfo auxcr = {
-            .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
-            .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
-            .access = PL1_RW, .type = ARM_CP_CONST,
-            .resetvalue = cpu->reset_auxcr
+        ARMCPRegInfo auxcr_reginfo[] = {
+            { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
+              .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
+              .access = PL1_RW, .type = ARM_CP_CONST,
+              .resetvalue = cpu->reset_auxcr },
+            { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
+              .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
+              .access = PL2_RW, .type = ARM_CP_CONST,
+              .resetvalue = 0 },
+            { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
+              .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
+              .access = PL3_RW, .type = ARM_CP_CONST,
+              .resetvalue = 0 },
+            REGINFO_SENTINEL
         };
-        define_one_arm_cp_reg(cpu, &auxcr);
+        define_arm_cp_regs(cpu, auxcr_reginfo);
     }
 
     if (arm_feature(env, ARM_FEATURE_CBAR)) {
-- 
1.9.1

Re: [Qemu-devel] [PATCH 0/4] target-arm: Implement missing EL3 (and EL2) registers

[Peter Maydell]

Ping?

thanks
-- PMM

On 30 July 2015 at 19:36, Peter Maydell <peter.maydell@linaro.org> wrote:
> This series adds a handful of EL3 system registers that
> we were missing. It also includes the EL2 flavours
> where there were obvious easy parallels. I think this
> means we now have all the EL3 sysregs we care about.
> (A previous series added missing address translation
> operations; I still have to do the missing TLB ops.)
>
> None of these registers are exciting; they're all either
> reads-as-written or RAZ/WI.
>
> A note for people who care about EL2: I notice that a
> lot of AArch32 EL2 registers have the access permission
> pattern of "accessible from EL2(NS) and from EL3 if
> SCR.NS==1, but traps if accessed from EL3 if SCR.NS==0".
> We don't implement this wrinkle (we won't trap the
> erroneous EL3 access). This is true of the EL2 regs I
> add here, but then it's true of all our existing ones...
>
> Peter Maydell (4):
>   target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
>   target-arm: Implement missing AMAIR registers
>   target-arm: Implement missing AFSR registers
>   target-arm: Implement missing ACTLR registers
>
>  target-arm/helper.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 68 insertions(+), 6 deletions(-)
>

Re: [Qemu-devel] [PATCH 0/4] target-arm: Implement missing EL3 (and EL2) registers

[Edgar E. Iglesias]

On Fri, Aug 14, 2015 at 11:12:55AM +0100, Peter Maydell wrote:
> Ping?
> 

Hi! Sorry for the delay! I'll have a look at this over the weekend.
Do you happen to have the patches all applied in a branch somewhere?

Thanks,
Edgar


> thanks
> -- PMM
> 
> On 30 July 2015 at 19:36, Peter Maydell <peter.maydell@linaro.org> wrote:
> > This series adds a handful of EL3 system registers that
> > we were missing. It also includes the EL2 flavours
> > where there were obvious easy parallels. I think this
> > means we now have all the EL3 sysregs we care about.
> > (A previous series added missing address translation
> > operations; I still have to do the missing TLB ops.)
> >
> > None of these registers are exciting; they're all either
> > reads-as-written or RAZ/WI.
> >
> > A note for people who care about EL2: I notice that a
> > lot of AArch32 EL2 registers have the access permission
> > pattern of "accessible from EL2(NS) and from EL3 if
> > SCR.NS==1, but traps if accessed from EL3 if SCR.NS==0".
> > We don't implement this wrinkle (we won't trap the
> > erroneous EL3 access). This is true of the EL2 regs I
> > add here, but then it's true of all our existing ones...
> >
> > Peter Maydell (4):
> >   target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
> >   target-arm: Implement missing AMAIR registers
> >   target-arm: Implement missing AFSR registers
> >   target-arm: Implement missing ACTLR registers
> >
> >  target-arm/helper.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++-----
> >  1 file changed, 68 insertions(+), 6 deletions(-)
> >

Re: [Qemu-devel] [PATCH 0/4] target-arm: Implement missing EL3 (and EL2) registers

[Peter Maydell]

On 14 August 2015 at 18:42, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> On Fri, Aug 14, 2015 at 11:12:55AM +0100, Peter Maydell wrote:
>> Ping?
>>
>
> Hi! Sorry for the delay! I'll have a look at this over the weekend.
> Do you happen to have the patches all applied in a branch somewhere?

Unfortunately not at the moment -- they're all separate
local branches (and I'll probably have to fix up the trivial
merge conflicts when I assemble them into target-arm.next).

-- PMM

Re: [Qemu-devel] [PATCH 0/4] target-arm: Implement missing EL3 (and EL2) registers

[Edgar E. Iglesias]

On Fri, Aug 14, 2015 at 06:48:28PM +0100, Peter Maydell wrote:
> On 14 August 2015 at 18:42, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> > On Fri, Aug 14, 2015 at 11:12:55AM +0100, Peter Maydell wrote:
> >> Ping?
> >>
> >
> > Hi! Sorry for the delay! I'll have a look at this over the weekend.
> > Do you happen to have the patches all applied in a branch somewhere?
> 
> Unfortunately not at the moment -- they're all separate
> local branches (and I'll probably have to fix up the trivial
> merge conflicts when I assemble them into target-arm.next).
>

OK, no worries. I'll see if can run some of it through our testsuites.

Cheers,
Edgar

Re: [Qemu-devel] [PATCH 1/4] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers

[Edgar E. Iglesias]

On Thu, Jul 30, 2015 at 07:36:35PM +0100, Peter Maydell wrote:
> Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only
> two which we had implemented the 32-bit Secure equivalents of but
> not the 64-bit Secure versions.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>



> ---
>  target-arm/helper.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 01f0d0d..d59616e 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1022,6 +1022,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
>        .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
>        .resetvalue = 0 },
> +    { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
> +      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
> +      .resetvalue = 0 },
>      /* For non-long-descriptor page tables these are PRRR and NMRR;
>       * regardless they still act as reads-as-written for QEMU.
>       */
> @@ -2790,6 +2794,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
>        .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
>        .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
> +    { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
> +      .access = PL3_RW, .resetvalue = 0,
> +      .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
>      REGINFO_SENTINEL
>  };
>  
> -- 
> 1.9.1
> 

Re: [Qemu-devel] [PATCH 2/4] target-arm: Implement missing AMAIR registers

[Edgar E. Iglesias]

On Thu, Jul 30, 2015 at 07:36:36PM +0100, Peter Maydell wrote:
> The AMAIR registers are for providing auxiliary implementation
> defined memory attributes. We already implemented a RAZ/WI
> AMAIR_EL1; add the EL2 and EL3 versions for consistency.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>


> ---
>  target-arm/helper.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d59616e..781b3a2 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2602,6 +2602,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>      { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
>        .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
> +    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
> +      .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> @@ -2696,6 +2704,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>        .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
>        .access = PL2_RW, .type = ARM_CP_ALIAS,
>        .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
> +    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
> +    /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
> +    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
> +      .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
>        .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
> @@ -2798,6 +2815,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
>        .access = PL3_RW, .resetvalue = 0,
>        .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
> +    { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
> +      .access = PL3_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      REGINFO_SENTINEL
>  };
>  
> -- 
> 1.9.1
> 

Re: [Qemu-devel] [PATCH 3/4] target-arm: Implement missing AFSR registers

[Edgar E. Iglesias]

On Thu, Jul 30, 2015 at 07:36:37PM +0100, Peter Maydell wrote:
> The AFSR registers are implementation dependent auxiliary fault
> status registers. We already implemented a RAZ/WI AFSR0_EL1 and
> AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>


> ---
>  target-arm/helper.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 781b3a2..d286680 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2610,6 +2610,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>        .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
>        .access = PL2_RW, .type = ARM_CP_CONST,
>        .resetvalue = 0 },
> +    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
> +    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> @@ -2713,6 +2721,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>        .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
>        .access = PL2_RW, .type = ARM_CP_CONST,
>        .resetvalue = 0 },
> +    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
> +    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
>        .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
> @@ -2819,6 +2835,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
>        .access = PL3_RW, .type = ARM_CP_CONST,
>        .resetvalue = 0 },
> +    { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
> +      .access = PL3_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
> +    { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
> +      .access = PL3_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      REGINFO_SENTINEL
>  };
>  
> -- 
> 1.9.1
> 

Re: [Qemu-devel] [PATCH 4/4] target-arm: Implement missing ACTLR registers

[Edgar E. Iglesias]

On Thu, Jul 30, 2015 at 07:36:38PM +0100, Peter Maydell wrote:
> We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and
> ACTLR_EL3, for consistency.
> 
> Since we don't currently have any CPUs that need the EL2/EL3
> versions to reset to non-zero values, implement as RAZ/WI.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>


> ---
>  target-arm/helper.c | 21 +++++++++++++++------
>  1 file changed, 15 insertions(+), 6 deletions(-)
> 
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d286680..b0b1a22 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3637,13 +3637,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>      }
>  
>      if (arm_feature(env, ARM_FEATURE_AUXCR)) {
> -        ARMCPRegInfo auxcr = {
> -            .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
> -            .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
> -            .access = PL1_RW, .type = ARM_CP_CONST,
> -            .resetvalue = cpu->reset_auxcr
> +        ARMCPRegInfo auxcr_reginfo[] = {
> +            { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
> +              .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
> +              .access = PL1_RW, .type = ARM_CP_CONST,
> +              .resetvalue = cpu->reset_auxcr },
> +            { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
> +              .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
> +              .access = PL2_RW, .type = ARM_CP_CONST,
> +              .resetvalue = 0 },
> +            { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
> +              .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
> +              .access = PL3_RW, .type = ARM_CP_CONST,
> +              .resetvalue = 0 },
> +            REGINFO_SENTINEL
>          };
> -        define_one_arm_cp_reg(cpu, &auxcr);
> +        define_arm_cp_regs(cpu, auxcr_reginfo);
>      }
>  
>      if (arm_feature(env, ARM_FEATURE_CBAR)) {
> -- 
> 1.9.1
>