From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44526) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZR67A-0001N9-R4 for qemu-devel@nongnu.org; Sun, 16 Aug 2015 18:09:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZR676-0001r2-2H for qemu-devel@nongnu.org; Sun, 16 Aug 2015 18:09:16 -0400 Received: from mail-pa0-x22f.google.com ([2607:f8b0:400e:c03::22f]:35033) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZR675-0001qo-QU for qemu-devel@nongnu.org; Sun, 16 Aug 2015 18:09:11 -0400 Received: by pacgr6 with SMTP id gr6so94236508pac.2 for ; Sun, 16 Aug 2015 15:09:11 -0700 (PDT) Date: Mon, 17 Aug 2015 00:09:09 +0200 From: "Edgar E. Iglesias" Message-ID: <20150816220909.GD16713@toto> References: <1438281398-18746-1-git-send-email-peter.maydell@linaro.org> <1438281398-18746-5-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1438281398-18746-5-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 4/4] target-arm: Implement missing ACTLR registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org On Thu, Jul 30, 2015 at 07:36:38PM +0100, Peter Maydell wrote: > We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and > ACTLR_EL3, for consistency. > > Since we don't currently have any CPUs that need the EL2/EL3 > versions to reset to non-zero values, implement as RAZ/WI. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/helper.c | 21 +++++++++++++++------ > 1 file changed, 15 insertions(+), 6 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index d286680..b0b1a22 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3637,13 +3637,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) > } > > if (arm_feature(env, ARM_FEATURE_AUXCR)) { > - ARMCPRegInfo auxcr = { > - .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, > - .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, > - .access = PL1_RW, .type = ARM_CP_CONST, > - .resetvalue = cpu->reset_auxcr > + ARMCPRegInfo auxcr_reginfo[] = { > + { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, > + .access = PL1_RW, .type = ARM_CP_CONST, > + .resetvalue = cpu->reset_auxcr }, > + { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, > + .access = PL2_RW, .type = ARM_CP_CONST, > + .resetvalue = 0 }, > + { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, > + .access = PL3_RW, .type = ARM_CP_CONST, > + .resetvalue = 0 }, > + REGINFO_SENTINEL > }; > - define_one_arm_cp_reg(cpu, &auxcr); > + define_arm_cp_regs(cpu, auxcr_reginfo); > } > > if (arm_feature(env, ARM_FEATURE_CBAR)) { > -- > 1.9.1 >