From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36818) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZR9aF-0000a4-RQ for qemu-devel@nongnu.org; Sun, 16 Aug 2015 21:51:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZR9aB-0005WG-M7 for qemu-devel@nongnu.org; Sun, 16 Aug 2015 21:51:31 -0400 Received: from mail-pa0-x235.google.com ([2607:f8b0:400e:c03::235]:36619) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZR9aB-0005Vz-B3 for qemu-devel@nongnu.org; Sun, 16 Aug 2015 21:51:27 -0400 Received: by pacum4 with SMTP id um4so11576875pac.3 for ; Sun, 16 Aug 2015 18:51:26 -0700 (PDT) Date: Mon, 17 Aug 2015 03:51:25 +0200 From: "Edgar E. Iglesias" Message-ID: <20150817015125.GF16713@toto> References: <1437751263-21913-1-git-send-email-peter.maydell@linaro.org> <1437751263-21913-3-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1437751263-21913-3-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 2/5] target-arm: Wire up AArch64 EL2 and EL3 address translation ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org On Fri, Jul 24, 2015 at 04:21:00PM +0100, Peter Maydell wrote: > Wire up the AArch64 EL2 and EL3 address translation operations > (AT S12E1*, AT S12E0*, AT S1E2*, AT S1E3*), and correct some > errors in the ats_write64() function in previously unused code > that would have done the wrong kind of lookup for accesses from > EL3 when SCR.NS==0. > > Signed-off-by: Peter Maydell THis one didn't apply for me, I guess some context has moved around a little.. The changes look OK to me though: Reviewed-by: Edgar E. Iglesias > --- > target-arm/helper.c | 45 +++++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 43 insertions(+), 2 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 1ac6594..1974fa6 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1602,6 +1602,14 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > A32_BANKED_CURRENT_REG_SET(env, par, par64); > } > > +static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri) > +{ > + if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { > + return CP_ACCESS_TRAP; > + } > + return CP_ACCESS_OK; > +} > + > static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > @@ -1629,10 +1637,10 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, > mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; > break; > case 4: /* AT S12E1R, AT S12E1W */ > - mmu_idx = ARMMMUIdx_S12NSE1; > + mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; > break; > case 6: /* AT S12E0R, AT S12E0W */ > - mmu_idx = ARMMMUIdx_S12NSE0; > + mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; > break; > default: > g_assert_not_reached(); > @@ -2504,6 +2512,25 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, > .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, > .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, > + { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 4, > + .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, > + { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 5, > + .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, > + { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6, > + .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, > + { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 7, > + .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, > + /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ > + { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, > + .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, > + { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, > + .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, > #endif > /* TLB invalidate last level of translation table walk */ > { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, > @@ -2724,6 +2751,20 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, > .type = ARM_CP_NO_RAW, .access = PL2_W, > .writefn = tlbi_aa64_vaa_write }, > +#ifndef CONFIG_USER_ONLY > + /* Unlike the other EL2-related AT operations, these must > + * UNDEF from EL3 if EL2 is not implemented, which is why we > + * define them here rather than with the rest of the AT ops. > + */ > + { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, > + .access = PL2_W, .accessfn = at_s1e2_access, > + .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, > + { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, > + .access = PL2_W, .accessfn = at_s1e2_access, > + .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, > +#endif > REGINFO_SENTINEL > }; > > -- > 1.9.1 >