From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55921) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZRRe5-0004il-Sf for qemu-devel@nongnu.org; Mon, 17 Aug 2015 17:08:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZRRe4-000240-Ai for qemu-devel@nongnu.org; Mon, 17 Aug 2015 17:08:41 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:35084) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZRRe4-00023e-4x for qemu-devel@nongnu.org; Mon, 17 Aug 2015 17:08:40 -0400 Date: Mon, 17 Aug 2015 23:08:37 +0200 From: Aurelien Jarno Message-ID: <20150817210837.GA20832@aurel32.net> References: <55B8B122.7020406@gmx.net> <55B8DB46.6070307@gmx.net> <55B99E47.8070007@gmx.net> <20150730075538.GU11361@aurel32.net> <55D2007F.3020607@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] Debian 7.8.0 SPARC64 on qemu - anything i can do to speedup the emulation? List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Artyom Tarasenko Cc: Karel Gardas , alex.bennee@linaro.org, qemu-devel , Dennis Luehring , Richard Henderson On 2015-08-17 18:25, Artyom Tarasenko wrote: > On Mon, Aug 17, 2015 at 5:40 PM, Richard Henderson wrote: > > On 08/17/2015 07:19 AM, Artyom Tarasenko wrote: > >> Well, on the other hand, every access goes via helper_check_align. > >> There is a comment /* XXX remove alignment check */. > >> I wonder how this can be done in a more efficient way? > > > > Not ever access does so. There are only 3 memory related calls to check_align. > > The other three are for indirect branches. > > Yes, but I think it's the 3 most used ones. > > > For the 8 byte memory operations we can just remove the checks. There, the > > softmmu operation checks the alignment. > > This is a good news. Where does it happen? > > > For usermode, we've typically ignored > > the guest alignment (which also causes failures for a host that requires > > alignment emulating a guest that does not). A tiny bit of topic, but couldn't we force the use of unaligned access load/store instructions in user mode instead? For example in QEMU we can use the LWL/LWR couple instead of LW. I doubt it will make any measurable difference in speed. For the MIPS case, that doesn't work for 16-bit load/stores though. The best would indeed be to switch to softmmu for the user mode. I know there are people working on that, but given that it might take time, it could be a simple temporary solution. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net