From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48413) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZWkqB-0000ZI-4T for qemu-devel@nongnu.org; Tue, 01 Sep 2015 08:39:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZWkq8-00089P-Ew for qemu-devel@nongnu.org; Tue, 01 Sep 2015 08:39:07 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40485) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZWkq8-00088w-An for qemu-devel@nongnu.org; Tue, 01 Sep 2015 08:39:04 -0400 Date: Tue, 1 Sep 2015 14:39:00 +0200 From: Igor Mammedov Message-ID: <20150901143900.44f43b44@nial.brq.redhat.com> In-Reply-To: <1440004102-4822-1-git-send-email-ehabkost@redhat.com> References: <1440004102-4822-1-git-send-email-ehabkost@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] target-i386: Disable cache info passthrough by default List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Eduardo Habkost Cc: Paolo Bonzini , qemu-devel@nongnu.org, =?UTF-8?B?QmVub8OudA==?= Canet On Wed, 19 Aug 2015 10:08:22 -0700 Eduardo Habkost wrote: > The host cache information may not make sense for the guest if the VM > CPU topology doesn't match the host CPU topology. To make sure we won't > expose broken cache information to the guest, disable cache info > passthrough by default, and add a new "host-cache-info" property that > can be used to enable the old behavior for users that really need it. >=20 > Cc: Beno=C3=AEt Canet > Signed-off-by: Eduardo Habkost > --- > target-i386/cpu.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) >=20 > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index cfb8aa7..3a71f15 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -689,7 +689,6 @@ struct X86CPUDefinition { > int stepping; > FeatureWordArray features; > char model_id[48]; > - bool cache_info_passthrough; > }; > =20 > static X86CPUDefinition builtin_x86_defs[] =3D { > @@ -1416,6 +1415,7 @@ static X86CPUDefinition host_cpudef; > =20 > static Property host_x86_cpu_properties[] =3D { > DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), > + DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, = false), > DEFINE_PROP_END_OF_LIST() > }; > =20 > @@ -1442,7 +1442,6 @@ static void host_x86_cpu_class_init(ObjectClass *oc= , void *data) > cpu_x86_fill_model_id(host_cpudef.model_id); > =20 > xcc->cpu_def =3D &host_cpudef; > - host_cpudef.cache_info_passthrough =3D true; > =20 > /* level, xlevel, xlevel2, and the feature words are initialized on > * instance_init, because they require KVM to be initialized. > @@ -2076,7 +2075,6 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDef= inition *def, Error **errp) > object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp= ); > object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp); > object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp); > - cpu->cache_info_passthrough =3D def->cache_info_passthrough; Isn't that a guest visible change? > object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp= ); > for (w =3D 0; w < FEATURE_WORDS; w++) { > env->features[w] =3D def->features[w];