From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Edgar Iglesias <edgar.iglesias@gmail.com>,
Peter Crosthwaite <crosthwaitepeter@gmail.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@xilinx.com>
Subject: Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value
Date: Fri, 4 Sep 2015 23:08:44 +0200 [thread overview]
Message-ID: <20150904210844.GB12618@toto> (raw)
In-Reply-To: <CAFEAcA-1qH45VjPBVe=t2Cn61S9BuvobJUWLpx9U6vWC=onQNA@mail.gmail.com>
On Fri, Sep 04, 2015 at 07:12:23PM +0100, Peter Maydell wrote:
> On 4 September 2015 at 19:00, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
> > On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias
> > <edgar.iglesias@xilinx.com> wrote:
> >> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
> >>> Bit 15 of the PHY Specific Status Register is reserved and
> >>> should remain 0. Fix the reset value to ensure that the 15th
> >>> bit is not set.
> >>>
> >>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> >>
> >> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> >
> > Thanks Edgar.
> >
> > Should this go via the ARM queue?
>
> I was planning to pick it up, unless Edgar would rather
> something else.
Sounds good if you take it Peter, thanks!
Best regards,
Edgar
next prev parent reply other threads:[~2015-09-04 21:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-03 22:10 [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value Alistair Francis
2015-09-03 22:56 ` Edgar E. Iglesias
2015-09-04 18:00 ` Alistair Francis
2015-09-04 18:12 ` Peter Maydell
2015-09-04 18:32 ` Alistair Francis
2015-09-04 21:08 ` Edgar E. Iglesias [this message]
2015-09-08 14:51 ` Peter Maydell
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