From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53845) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZY0FG-0002cH-Ra for qemu-devel@nongnu.org; Fri, 04 Sep 2015 19:18:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZY0FD-00025J-LZ for qemu-devel@nongnu.org; Fri, 04 Sep 2015 19:18:10 -0400 Received: from mail-bn1bon0060.outbound.protection.outlook.com ([157.56.111.60]:22240 helo=na01-bn1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZY0FD-00024L-EE for qemu-devel@nongnu.org; Fri, 04 Sep 2015 19:18:07 -0400 Date: Sat, 5 Sep 2015 01:18:03 +0200 From: "Edgar E. Iglesias" Message-ID: <20150904231803.GC12618@toto> References: <1441383782-24378-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1441383782-24378-1-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH v3 0/6] ARM: enable TZ in the GIC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "Edgar E. Iglesias" , qemu-devel@nongnu.org, patches@linaro.org On Fri, Sep 04, 2015 at 05:22:56PM +0100, Peter Maydell wrote: > This patchset enables the TZ support in the GIC for the systems > where we enable TZ support in the CPU. In practice that means > just the "virt" and "vexpress" boards, since all the others > disable the CPU TZ support. > > There are no changes since v3, I've just rebased this all on > top of current target-arm.next (which will be in master early > next week as I've just sent out the pullreq). > > These have already been reviewed by Peter C, but when I spoke > to Edgar at KVM Forum he said he hadn't been able to sort out > which tree these would apply to, so I figured I'd better resend > them so there's a chance for further review/testing if desired. > Thanks Peter, Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Cheers, Edgar > thanks > -- PMM > > Changes since v2: > * rebased onto target-arm.next > Changes since v1: > * New patch which switches the default for the 'virt' board from > "enable TZ" to "disable TZ". The UEFI blob can't handle TZ being > fully enabled, so I had a choice of breaking it or breaking code > which assumes TZ. As far as I know only the TZ test suite falls > in the latter category. -machine secure=on will give you the > old behaviour back. > * rather than the property on the GIC, we take the approach Peter C > suggested of defining an interface for devices to implement if > they need to do firmware-equivalent setup. The API is a little > different from Peter C's RFC patch, but the principle is the same. > > > > Peter Crosthwaite (1): > qom: Add recursive version of object_child_for_each > > Peter Maydell (5): > hw/arm: new interface for devices which need to behave differently for > kernel boot > hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel > boot > hw/cpu/{a15mpcore,a9mpcore}: enable TrustZone in GIC if it is enabled > in CPUs > hw/arm/virt: Default to not providing TrustZone support > hw/arm/virt: Enable TZ extensions on the GIC if we are using them > > hw/arm/boot.c | 34 +++++++++++++++++++++++++++ > hw/arm/virt.c | 14 +++++++---- > hw/cpu/a15mpcore.c | 13 ++++++++++ > hw/cpu/a9mpcore.c | 11 +++++++++ > hw/intc/arm_gic_common.c | 51 +++++++++++++++++++++++++++++++++++++--- > include/hw/arm/linux-boot-if.h | 43 +++++++++++++++++++++++++++++++++ > include/hw/intc/arm_gic_common.h | 1 + > include/qom/object.h | 15 ++++++++++++ > qom/object.c | 25 +++++++++++++++++--- > 9 files changed, 197 insertions(+), 10 deletions(-) > create mode 100644 include/hw/arm/linux-boot-if.h > > -- > 1.9.1 >