Re: [Qemu-devel] [PATCH v1 04/10] target-arm: Add VTCR_EL2

["Edgar E. Iglesias" <edgar.iglesias@xilinx.com>]

On Tue, Sep 08, 2015 at 03:19:37PM +0100, Peter Maydell wrote:
> On 3 September 2015 at 21:14, Edgar E. Iglesias
> <edgar.iglesias@gmail.com> wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> >  target-arm/cpu.h    |  1 +
> >  target-arm/helper.c | 28 ++++++++++++++++++++++++++--
> >  2 files changed, 27 insertions(+), 2 deletions(-)
> >
> > diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> > index 31825d3..ba22e12 100644
> > --- a/target-arm/cpu.h
> > +++ b/target-arm/cpu.h
> > @@ -223,6 +223,7 @@ typedef struct CPUARMState {
> >          };
> >          /* MMU translation table base control. */
> >          TCR tcr_el[4];
> > +        TCR vtcr_el2; /* Virtualization Translation Control.  */
> >          uint32_t c2_data; /* MPU data cachable bits.  */
> >          uint32_t c2_insn; /* MPU instruction cachable bits.  */
> >          union { /* MMU domain access control register
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index a057a70..c82aa1d 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -325,6 +325,21 @@ void init_cpreg_list(ARMCPU *cpu)
> >      g_list_free(keys);
> >  }
> >
> > +/*
> > + * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
> > + * they are accesible when EL3 is using AArch64 regardless of EL3.NS.
> > + */
> > +static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
> > +                                                const ARMCPRegInfo *ri)
> > +{
> > +    bool secure = arm_is_secure_below_el3(env);
> > +
> > +    if (secure && !arm_el_is_aa64(env, 3)) {
> > +        return CP_ACCESS_TRAP_UNCATEGORIZED;
> > +    }
> > +    return CP_ACCESS_OK;
> > +}
> 
> This access function will always return OK for the AArch64 register,
> so probably better to split the regdef rather than using STATE_BOTH,
> and then avoid the accessfn on the 64-bit register.


Hi Peter,

In the interest avoiding duplication, do you think the following makes
sense for regs with the el3_aa32ns_aa64any access checks?

1. Use STATE_BOTH for "low-activity" registers (e.g the EL3 view when EL2 does not exist).
2. Use STATE_BOTH for regs that anyway have a read/write function
3. Split AA64 and AA32 reg entries for regs without read/write helper call for spead (e.g VTCR_EL2).

Cheers,
Edgar