From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59190) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbZHf-0005DI-BS for qemu-devel@nongnu.org; Mon, 14 Sep 2015 15:19:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZbZHd-0008CS-TZ for qemu-devel@nongnu.org; Mon, 14 Sep 2015 15:19:23 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:36747) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbZHd-0008C1-Np for qemu-devel@nongnu.org; Mon, 14 Sep 2015 15:19:21 -0400 Date: Mon, 14 Sep 2015 21:19:18 +0200 From: Aurelien Jarno Message-ID: <20150914191918.GA26503@aurel32.net> References: <1442234994-15841-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1442234994-15841-1-git-send-email-leon.alrae@imgtec.com> Subject: Re: [Qemu-devel] [PATCH] target-mips: add missing restriction in DAUI instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae Cc: qemu-devel@nongnu.org On 2015-09-14 13:49, Leon Alrae wrote: > rs cannot be the zero register, Reserved Instruction exception must be > signalled for this case. > > Signed-off-by: Leon Alrae > --- > target-mips/translate.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 7fb7c01..a8fd4a3 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -19512,7 +19512,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) > #if defined(TARGET_MIPS64) > /* OPC_DAUI */ > check_mips_64(ctx); > - if (rt != 0) { > + if (rs == 0) { > + generate_exception(ctx, EXCP_RI); > + } else if (rt != 0) { > TCGv t0 = tcg_temp_new(); > gen_load_gpr(t0, rs); > tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16); Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net