From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37001) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zcv34-0007B1-AS for qemu-devel@nongnu.org; Fri, 18 Sep 2015 08:45:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zcv2z-0004Cq-7x for qemu-devel@nongnu.org; Fri, 18 Sep 2015 08:45:54 -0400 Received: from indium.canonical.com ([91.189.90.7]:34603) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zcv2z-0004CF-3B for qemu-devel@nongnu.org; Fri, 18 Sep 2015 08:45:49 -0400 Received: from loganberry.canonical.com ([91.189.90.37]) by indium.canonical.com with esmtp (Exim 4.76 #1 (Debian)) id 1Zcv2y-0000jH-8V for ; Fri, 18 Sep 2015 12:45:48 +0000 Received: from loganberry.canonical.com (localhost [127.0.0.1]) by loganberry.canonical.com (Postfix) with ESMTP id 2FDBC2E80BB for ; Fri, 18 Sep 2015 12:45:48 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Date: Fri, 18 Sep 2015 12:37:08 -0000 From: PeteVine Sender: bounces@canonical.com References: <20150627003937.6939.65806.malonedeb@gac.canonical.com> Message-Id: <20150918123708.12829.99417.malone@soybean.canonical.com> Errors-To: bounces@canonical.com Subject: [Qemu-devel] [Bug 1469342] Re: qemu-i386 pentium3 incorrect instruction set Reply-To: Bug 1469342 <1469342@bugs.launchpad.net> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Still there in the latest master. To clarify, running the binary with the -cpu athlon switch (same instruction set as P3) also exhibits the problem whereas a real athlon SIGILL's correctly. ** Description changed: Running a binary containing a movsd instruction (SSE2) in 32-bit - qemu-i386 -cpu pentium3 from 20150609 results in flawless execution - whereas it should crash with SIGILL as P3 only had SSE. + qemu-i386 from 20150609 using the -cpu pentium3 switch results in + flawless execution whereas it should crash with SIGILL as P3 only had + SSE and not SSE2. ** Summary changed: - qemu-i386 pentium3 incorrect instruction set + qemu-i386 pentium3/athlon incorrect instruction set -- = You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1469342 Title: qemu-i386 pentium3/athlon incorrect instruction set Status in QEMU: New Bug description: Running a binary containing a movsd instruction (SSE2) in 32-bit qemu-i386 from 20150609 using the -cpu pentium3 switch results in flawless execution whereas it should crash with SIGILL as P3 only had SSE and not SSE2. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1469342/+subscriptions