[Qemu-devel] [Bug 1469342] [NEW] qemu-i386 pentium3 incorrect instruction set

[Qemu-devel] [Bug 1469342] [NEW] qemu-i386 pentium3 incorrect instruction set

[PeteVine]

Public bug reported:

Running a binary containing a movsd instruction (SSE2) in 32-bit
qemu-i386 -cpu pentium3 from 20150609 results in flawless execution
whereas it should crash with SIGILL as P3 only had SSE.

** Affects: qemu
     Importance: Undecided
         Status: New

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Title:
  qemu-i386 pentium3 incorrect instruction set

Status in QEMU:
  New

Bug description:
  Running a binary containing a movsd instruction (SSE2) in 32-bit
  qemu-i386 -cpu pentium3 from 20150609 results in flawless execution
  whereas it should crash with SIGILL as P3 only had SSE.

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[Qemu-devel] [Bug 1469342] Re: qemu-i386 pentium3 incorrect instruction set

[PeteVine]

Still there in the latest master.

To clarify, running the binary with the -cpu athlon switch (same
instruction set as P3) also exhibits the problem whereas a real athlon
SIGILL's correctly.

** Description changed:

  Running a binary containing a movsd instruction (SSE2) in 32-bit
- qemu-i386 -cpu pentium3 from 20150609 results in flawless execution
- whereas it should crash with SIGILL as P3 only had SSE.
+ qemu-i386 from 20150609 using the -cpu pentium3 switch results in
+ flawless execution whereas it should crash with SIGILL as P3 only had
+ SSE and not SSE2.

** Summary changed:

- qemu-i386 pentium3 incorrect instruction set
+ qemu-i386 pentium3/athlon incorrect instruction set

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https://bugs.launchpad.net/bugs/1469342

Title:
  qemu-i386 pentium3/athlon incorrect instruction set

Status in QEMU:
  New

Bug description:
  Running a binary containing a movsd instruction (SSE2) in 32-bit
  qemu-i386 from 20150609 using the -cpu pentium3 switch results in
  flawless execution whereas it should crash with SIGILL as P3 only had
  SSE and not SSE2.

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[Qemu-devel] [Bug 1469342] Re: qemu-i386 pentium3/athlon incorrect instruction set

[Paolo Bonzini]

QEMU doesn't try to mimic the exact set of instructions for a processor,
unfortunately. Virtualization solutions like KVM also do not allow you
to do that, so the case for this feature is relatively minor.

However, patches are welcome.

** Changed in: qemu
       Status: New => Won't Fix

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Title:
  qemu-i386 pentium3/athlon incorrect instruction set

Status in QEMU:
  Won't Fix

Bug description:
  Running a binary containing a movsd instruction (SSE2) in 32-bit
  qemu-i386 from 20150609 using the -cpu pentium3 switch results in
  flawless execution whereas it should crash with SIGILL as P3 only had
  SSE and not SSE2.

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[Qemu-devel] [Bug 1469342] Re: qemu-i386 pentium3/athlon incorrect instruction set

[PeteVine]

I'm pretty sure you're right regarding entire instruction sets - but
surely simply disabling SSE2 is possible even now? (after all pentium2
and below doesn't have it)

That could solve this problem with a simple hack like, eg. :

pentium3 = $pentium3 - SSE2

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https://bugs.launchpad.net/bugs/1469342

Title:
  qemu-i386 pentium3/athlon incorrect instruction set

Status in QEMU:
  Won't Fix

Bug description:
  Running a binary containing a movsd instruction (SSE2) in 32-bit
  qemu-i386 from 20150609 using the -cpu pentium3 switch results in
  flawless execution whereas it should crash with SIGILL as P3 only had
  SSE and not SSE2.

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[Qemu-devel] [Bug 1469342] Re: qemu-i386 pentium3/athlon incorrect instruction set

[PeteVine]

In the case it's really unfixable and both pentium3 and athlon are
nothing more than aliases for 'QEMU Virtual CPU version 2.4.50' they
should be removed from the list the user gets after:

qemu-i386 -cpu help

so as not to mislead. Thanks!

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Title:
  qemu-i386 pentium3/athlon incorrect instruction set

Status in QEMU:
  Won't Fix

Bug description:
  Running a binary containing a movsd instruction (SSE2) in 32-bit
  qemu-i386 from 20150609 using the -cpu pentium3 switch results in
  flawless execution whereas it should crash with SIGILL as P3 only had
  SSE and not SSE2.

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[Qemu-devel] [Bug 1469342] Re: qemu-i386 pentium3/athlon incorrect instruction set

[PeteVine]

After looking at target-i386/cpu.c, it's clear to me CPUID_SSE and
CPUID_SSE2 are defined seperately and neither pentium3 nor athlon have
those defines set.

This could mean it's a bug not in the instruction set but possibly in
the build process somewhere.

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Title:
  qemu-i386 pentium3/athlon incorrect instruction set

Status in QEMU:
  Won't Fix

Bug description:
  Running a binary containing a movsd instruction (SSE2) in 32-bit
  qemu-i386 from 20150609 using the -cpu pentium3 switch results in
  flawless execution whereas it should crash with SIGILL as P3 only had
  SSE and not SSE2.

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[Qemu-devel] [Bug 1469342] Re: qemu-i386 pentium3/athlon incorrect instruction set

[Marina Kovalevna]

This option is useful for testing, nothing more.

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https://bugs.launchpad.net/bugs/1469342

Title:
  qemu-i386 pentium3/athlon incorrect instruction set

Status in QEMU:
  Won't Fix

Bug description:
  Running a binary containing a movsd instruction (SSE2) in 32-bit
  qemu-i386 from 20150609 using the -cpu pentium3 switch results in
  flawless execution whereas it should crash with SIGILL as P3 only had
  SSE and not SSE2.

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[Qemu-devel] [Bug 1469342] Re: qemu-i386 pentium3/athlon incorrect instruction set

[PeteVine]

I think I may have found the culprit - athlon is defined as
'PPRO_FEATURES + some additional features'.

If  PPRO_FEATURES is what I think it is (pentium pro) why does it have
SSE and SSE2 defined? It should end with MMX.

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Title:
  qemu-i386 pentium3/athlon incorrect instruction set

Status in QEMU:
  Won't Fix

Bug description:
  Running a binary containing a movsd instruction (SSE2) in 32-bit
  qemu-i386 from 20150609 using the -cpu pentium3 switch results in
  flawless execution whereas it should crash with SIGILL as P3 only had
  SSE and not SSE2.

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