From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47135) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhUGm-0000ut-Nz for qemu-devel@nongnu.org; Wed, 30 Sep 2015 23:10:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZhUGk-0004d6-V3 for qemu-devel@nongnu.org; Wed, 30 Sep 2015 23:10:56 -0400 Date: Thu, 1 Oct 2015 13:11:14 +1000 From: David Gibson Message-ID: <20151001031114.GJ23574@voom> References: <1443625999-2306-1-git-send-email-lvivier@redhat.com> <1443625999-2306-2-git-send-email-lvivier@redhat.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="Do4IU1xF/9sod/r6" Content-Disposition: inline In-Reply-To: <1443625999-2306-2-git-send-email-lvivier@redhat.com> Subject: Re: [Qemu-devel] [PATCH v5 1/2] PCI: add missing classes in pci_ids.h to build device tree List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Laurent Vivier Cc: thuth@redhat.com, "Michael S. Tsirkin" , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org --Do4IU1xF/9sod/r6 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Sep 30, 2015 at 05:13:18PM +0200, Laurent Vivier wrote: > To allow QEMU to add PCI entries in device tree, > we must have a more exhaustive list of PCI class IDs. >=20 > This patch synchronizes as much as possible with > pci_ids.h and add some missing IDs from SLOF. >=20 > Signed-off-by: Laurent Vivier > Reviewed-by: Michael S. Tsirkin > Reviewed-by: Thomas Huth Michael, Should I take this through my tree, or do you want to take it through yours? If the first, can I get an Acked-by? > --- > include/hw/pci/pci_ids.h | 112 +++++++++++++++++++++++++++++++++++++++++= ++---- > 1 file changed, 103 insertions(+), 9 deletions(-) >=20 > diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h > index d98e6c9..e27dc39 100644 > --- a/include/hw/pci/pci_ids.h > +++ b/include/hw/pci/pci_ids.h > @@ -12,41 +12,84 @@ > =20 > /* Device classes and subclasses */ > =20 > -#define PCI_BASE_CLASS_STORAGE 0x01 > -#define PCI_BASE_CLASS_NETWORK 0x02 > +#define PCI_CLASS_NOT_DEFINED 0x0000 > +#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 > =20 > +#define PCI_BASE_CLASS_STORAGE 0x01 > #define PCI_CLASS_STORAGE_SCSI 0x0100 > #define PCI_CLASS_STORAGE_IDE 0x0101 > +#define PCI_CLASS_STORAGE_FLOPPY 0x0102 > +#define PCI_CLASS_STORAGE_IPI 0x0103 > #define PCI_CLASS_STORAGE_RAID 0x0104 > +#define PCI_CLASS_STORAGE_ATA 0x0105 > #define PCI_CLASS_STORAGE_SATA 0x0106 > +#define PCI_CLASS_STORAGE_SAS 0x0107 > #define PCI_CLASS_STORAGE_EXPRESS 0x0108 > #define PCI_CLASS_STORAGE_OTHER 0x0180 > =20 > +#define PCI_BASE_CLASS_NETWORK 0x02 > #define PCI_CLASS_NETWORK_ETHERNET 0x0200 > +#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 > +#define PCI_CLASS_NETWORK_FDDI 0x0202 > +#define PCI_CLASS_NETWORK_ATM 0x0203 > +#define PCI_CLASS_NETWORK_ISDN 0x0204 > +#define PCI_CLASS_NETWORK_WORLDFIP 0x0205 > +#define PCI_CLASS_NETWORK_PICMG214 0x0206 > #define PCI_CLASS_NETWORK_OTHER 0x0280 > =20 > +#define PCI_BASE_CLASS_DISPLAY 0x03 > #define PCI_CLASS_DISPLAY_VGA 0x0300 > +#define PCI_CLASS_DISPLAY_XGA 0x0301 > +#define PCI_CLASS_DISPLAY_3D 0x0302 > #define PCI_CLASS_DISPLAY_OTHER 0x0380 > =20 > +#define PCI_BASE_CLASS_MULTIMEDIA 0x04 > +#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 > #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 > +#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 > +#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 > =20 > +#define PCI_BASE_CLASS_MEMORY 0x05 > #define PCI_CLASS_MEMORY_RAM 0x0500 > +#define PCI_CLASS_MEMORY_FLASH 0x0501 > +#define PCI_CLASS_MEMORY_OTHER 0x0580 > =20 > -#define PCI_CLASS_SYSTEM_SDHCI 0x0805 > -#define PCI_CLASS_SYSTEM_OTHER 0x0880 > - > -#define PCI_CLASS_SERIAL_USB 0x0c03 > -#define PCI_CLASS_SERIAL_SMBUS 0x0c05 > - > +#define PCI_BASE_CLASS_BRIDGE 0x06 > #define PCI_CLASS_BRIDGE_HOST 0x0600 > #define PCI_CLASS_BRIDGE_ISA 0x0601 > +#define PCI_CLASS_BRIDGE_EISA 0x0602 > +#define PCI_CLASS_BRIDGE_MC 0x0603 > #define PCI_CLASS_BRIDGE_PCI 0x0604 > #define PCI_CLASS_BRIDGE_PCI_INF_SUB 0x01 > +#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 > +#define PCI_CLASS_BRIDGE_NUBUS 0x0606 > +#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 > +#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 > +#define PCI_CLASS_BRIDGE_PCI_SEMITP 0x0609 > +#define PCI_CLASS_BRIDGE_IB_PCI 0x060a > #define PCI_CLASS_BRIDGE_OTHER 0x0680 > =20 > +#define PCI_BASE_CLASS_COMMUNICATION 0x07 > #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 > +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 > +#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 > +#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 > +#define PCI_CLASS_COMMUNICATION_GPIB 0x0704 > +#define PCI_CLASS_COMMUNICATION_SC 0x0705 > #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 > =20 > +#define PCI_BASE_CLASS_SYSTEM 0x08 > +#define PCI_CLASS_SYSTEM_PIC 0x0800 > +#define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 > +#define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 > +#define PCI_CLASS_SYSTEM_DMA 0x0801 > +#define PCI_CLASS_SYSTEM_TIMER 0x0802 > +#define PCI_CLASS_SYSTEM_RTC 0x0803 > +#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 > +#define PCI_CLASS_SYSTEM_SDHCI 0x0805 > +#define PCI_CLASS_SYSTEM_OTHER 0x0880 > + > +#define PCI_BASE_CLASS_INPUT 0x09 > #define PCI_CLASS_INPUT_KEYBOARD 0x0900 > #define PCI_CLASS_INPUT_PEN 0x0901 > #define PCI_CLASS_INPUT_MOUSE 0x0902 > @@ -54,8 +97,59 @@ > #define PCI_CLASS_INPUT_GAMEPORT 0x0904 > #define PCI_CLASS_INPUT_OTHER 0x0980 > =20 > -#define PCI_CLASS_PROCESSOR_CO 0x0b40 > +#define PCI_BASE_CLASS_DOCKING 0x0a > +#define PCI_CLASS_DOCKING_GENERIC 0x0a00 > +#define PCI_CLASS_DOCKING_OTHER 0x0a80 > + > +#define PCI_BASE_CLASS_PROCESSOR 0x0b > +#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 > #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 > +#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 > +#define PCI_CLASS_PROCESSOR_CO 0x0b40 > + > +#define PCI_BASE_CLASS_SERIAL 0x0c > +#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 > +#define PCI_CLASS_SERIAL_ACCESS 0x0c01 > +#define PCI_CLASS_SERIAL_SSA 0x0c02 > +#define PCI_CLASS_SERIAL_USB 0x0c03 > +#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 > +#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 > +#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 > +#define PCI_CLASS_SERIAL_USB_XHCI 0x0c0330 > +#define PCI_CLASS_SERIAL_USB_UNKNOWN 0x0c0380 > +#define PCI_CLASS_SERIAL_USB_DEVICE 0x0c03fe > +#define PCI_CLASS_SERIAL_FIBER 0x0c04 > +#define PCI_CLASS_SERIAL_SMBUS 0x0c05 > +#define PCI_CLASS_SERIAL_IB 0x0c06 > +#define PCI_CLASS_SERIAL_IPMI 0x0c07 > +#define PCI_CLASS_SERIAL_SERCOS 0x0c08 > +#define PCI_CLASS_SERIAL_CANBUS 0x0c09 > + > +#define PCI_BASE_CLASS_WIRELESS 0x0d > +#define PCI_CLASS_WIRELESS_IRDA 0x0d00 > +#define PCI_CLASS_WIRELESS_CIR 0x0d01 > +#define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 > +#define PCI_CLASS_WIRELESS_BLUETOOTH 0x0d11 > +#define PCI_CLASS_WIRELESS_BROADBAND 0x0d12 > +#define PCI_CLASS_WIRELESS_OTHER 0x0d80 > + > +#define PCI_BASE_CLASS_SATELLITE 0x0f > +#define PCI_CLASS_SATELLITE_TV 0x0f00 > +#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 > +#define PCI_CLASS_SATELLITE_VOICE 0x0f03 > +#define PCI_CLASS_SATELLITE_DATA 0x0f04 > + > +#define PCI_BASE_CLASS_CRYPT 0x10 > +#define PCI_CLASS_CRYPT_NETWORK 0x1000 > +#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 > +#define PCI_CLASS_CRYPT_OTHER 0x1080 > + > +#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 > +#define PCI_CLASS_SP_DPIO 0x1100 > +#define PCI_CLASS_SP_PERF 0x1101 > +#define PCI_CLASS_SP_SYNCH 0x1110 > +#define PCI_CLASS_SP_MANAGEMENT 0x1120 > +#define PCI_CLASS_SP_OTHER 0x1180 > =20 > #define PCI_CLASS_OTHERS 0xff > =20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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