From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54527) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zhpwj-0002fy-Kc for qemu-devel@nongnu.org; Thu, 01 Oct 2015 22:19:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zhpwf-0004c6-Mw for qemu-devel@nongnu.org; Thu, 01 Oct 2015 22:19:41 -0400 Received: from mail-pa0-x232.google.com ([2607:f8b0:400e:c03::232]:36077) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhokK-0004tc-U5 for qemu-devel@nongnu.org; Thu, 01 Oct 2015 21:02:49 -0400 Received: by pablk4 with SMTP id lk4so89774993pab.3 for ; Thu, 01 Oct 2015 18:02:48 -0700 (PDT) Date: Thu, 1 Oct 2015 18:02:45 -0700 From: "Edgar E. Iglesias" Message-ID: <20151002010245.GA9221@toto> References: <5eded8311c4c16ac22956810a68497424d9ee62c.1437612120.git.alistair.francis@xilinx.com> <20150725024508.GB3976@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150725024508.GB3976@toto> Subject: Re: [Qemu-devel] [PATCH v1 1/1] target-microblaze: Set the PC in reset instead of realize List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis Cc: edgar.iglesias@xilinx.com, crosthwaitepeter@gmail.com, qemu-devel@nongnu.org On Sat, Jul 25, 2015 at 12:45:08PM +1000, Edgar E. Iglesias wrote: > On Thu, Jul 23, 2015 at 08:13:56AM -0700, Alistair Francis wrote: > > Set the Microblaze CPU PC in the reset instead of setting it > > in the realize. This is required as the PC is zeroed in the > > reset function and causes problems in some situations. > > > > Signed-off-by: Alistair Francis > > Looks good: > > Reviewed-by: Edgar E. Iglesias > > I'll test and add this to my queue. Applied, thanks! (Sorry for the delay...) > > > > --- > > > > target-microblaze/cpu.c | 4 ++-- > > 1 files changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c > > index 9ac509a..cbd84a2 100644 > > --- a/target-microblaze/cpu.c > > +++ b/target-microblaze/cpu.c > > @@ -107,6 +107,8 @@ static void mb_cpu_reset(CPUState *s) > > /* Disable stack protector. */ > > env->shr = ~0; > > > > + env->sregs[SR_PC] = cpu->cfg.base_vectors; > > + > > #if defined(CONFIG_USER_ONLY) > > /* start in user mode with interrupts enabled. */ > > env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; > > @@ -183,8 +185,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) > > env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ > > env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); > > > > - env->sregs[SR_PC] = cpu->cfg.base_vectors; > > - > > mcc->parent_realize(dev, errp); > > } > > > > -- > > 1.7.1 > >