From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57777) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZiU5C-00044X-Or for qemu-devel@nongnu.org; Sat, 03 Oct 2015 17:11:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZiU59-0007tF-EJ for qemu-devel@nongnu.org; Sat, 03 Oct 2015 17:11:06 -0400 Received: from mail-pa0-x232.google.com ([2607:f8b0:400e:c03::232]:34669) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZiU59-0007t7-8i for qemu-devel@nongnu.org; Sat, 03 Oct 2015 17:11:03 -0400 Received: by padhy16 with SMTP id hy16so137873219pad.1 for ; Sat, 03 Oct 2015 14:11:02 -0700 (PDT) Date: Sat, 3 Oct 2015 14:11:00 -0700 From: "Edgar E. Iglesias" Message-ID: <20151003211100.GE24839@toto> References: <1443746968-9389-1-git-send-email-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1443746968-9389-1-git-send-email-edgar.iglesias@gmail.com> Subject: Re: [Qemu-devel] [PATCH v2 0/8] arm: Steps towards EL2 support round 5 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de On Thu, Oct 01, 2015 at 05:49:20PM -0700, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Hi, > > Another round of patches towards EL2 support. This one adds partial > support for 2-stage MMU for AArch64. I've marked it RFC because I > expect a few iterations. Once we can settle on the approach I'll > add the AArch32 support (changes for arm_ldl_ptw etc). I've probably > missed alot of details aswell. > > Some of the details of error reporting are intentionally missing, I > was thinking to add those incrementally as they get quite involved > (e.g the register target and memory access size). > > Some of the patches at the start of the series might be good already, > please pick them up if you agree Peter! > > Comments welcome! Please ignore this v2, I'll be sending a v3 shortly... Cheers, Edgar > > Best regards, > Edgar > > v1 -> v2: > * Fix HPFAR_EL2 access checks > * Prettify computation of starting level for S2 PTW > * Improve description of ap argument to get_S2prot > * Fix EXEC protection in get_S2prot > * Improve comments on S2 PTW attribute extraction > > Edgar E. Iglesias (8): > target-arm: Add HPFAR_EL2 > target-arm: Add computation of starting level for S2 PTW > target-arm: Add support for S2 page-table protection bits > target-arm: Avoid inline for get_phys_addr > target-arm: Add ARMMMUFaultInfo > target-arm: Add S2 translation support for S1 PTW > target-arm: Route S2 MMU faults to EL2 > target-arm: Add support for S1 + S2 MMU translations > > target-arm/cpu.h | 1 + > target-arm/helper.c | 216 ++++++++++++++++++++++++++++++++++++++++--------- > target-arm/internals.h | 11 ++- > target-arm/op_helper.c | 17 ++-- > 4 files changed, 200 insertions(+), 45 deletions(-) > > -- > 1.9.1 >