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Date: Sun, 4 Oct 2015 21:56:57 +0200
From: Beniamino Galvani <b.galvani@gmail.com>
Message-ID: <20151004195627.GA17883@gmail.com>
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Subject: Re: [Qemu-devel] QEMU+Linux ARMv7A current state
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To: Peter Crosthwaite <crosthwaitepeter@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>, Rob Herring <rob.herring@linaro.org>, Igor Mitsyanko <i.mitsyanko@gmail.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Nathan Rossi <nathan@nathanrossi.com>, Sai Pavan Boddu <saipava@xilinx.com>, Richard Purdie <richard.purdie@linuxfoundation.org>, Alistair Francis <alistair.francis@xilinx.com>, John Snow <jsnow@redhat.com>, Guenter Roeck <linux@roeck-us.net>

On Sat, Oct 03, 2015 at 02:31:08PM -0700, Peter Crosthwaite wrote:
> QEMU cubieboard has no usable storage media, but the real hardware
> does have AHCI sata. I added sysbus-ahci at the right place but turns
> out the SATA controller has some custom power/clock (not really
> sure??) registers specific to this SoC. It sets/clears bits then polls
> them back expecting them to change to the other value asynchronously.
> The kernel device probe then times-out. So I subclassed sysbus-ahci
> and added the missing registers and forced the polled registers to the
> "I'm done" state. It works.

Cool, are you going to submit patches for this?

> I am using meta-sunxi Yocto-layer to build out the allwinner custom
> kernel/rootfs etc, and with the clock and Sata changes I get a boot.
> But when I change to the unedited kernel+dtb+rootfs I get stuck. RTC
> messages are around the point of failure which is not modelled in
> QEMU, so that is suspect.

I don't know, this needs some investigation; on my side a recent
multi_v7_defconfig kernel, unmodified sun4i-a10-cubieboard.dtb and a
rootfs built with buildroot mounted through NFS work just fine, with
the mentioned warnings regarding clk registers and also these:

Ignoring attempt to switch CPSR_A flag from non-secure world with SCR.AW bit clear
Ignoring attempt to switch CPSR_F flag from non-secure world with SCR.FW bit clear

which probably would be solved by setting the property 'has_el3' of
the CPU to false before realization.

Beniamino