From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56731) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zm36q-0005EK-9s for qemu-devel@nongnu.org; Tue, 13 Oct 2015 13:11:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zm36o-0000zp-Nh for qemu-devel@nongnu.org; Tue, 13 Oct 2015 13:11:32 -0400 From: =?utf-8?b?TGx1w61z?= Vilanova Date: Tue, 13 Oct 2015 19:10:55 +0200 Message-Id: <20151013171055.21325.77814.stgit@localhost> In-Reply-To: <20151013171020.21325.27626.stgit@localhost> References: <20151013171020.21325.27626.stgit@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCHv16/8] exec: [tcg] Track which vCPU is performing translation and execution List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Guan Xuetao , Eduardo Habkost , Stefan Hajnoczi , Anthony Green , Mark Cave-Ayland , Jia Liu , Alexander Graf , Blue Swirl , Max Filippov , Michael Walle , "open list:PowerPC" , "Edgar E. Iglesias" , Paolo Bonzini , Bastian Koppelmann , Leon Alrae , Aurelien Jarno , Richard Henderson Information is tracked inside the TCGContext structure. Signed-off-by: Llu=C3=ADs Vilanova --- target-alpha/translate.c | 1 + target-arm/translate.c | 1 + target-cris/translate.c | 1 + target-cris/translate_v10.c | 1 + target-i386/translate.c | 1 + target-lm32/translate.c | 1 + target-m68k/translate.c | 1 + target-microblaze/translate.c | 1 + target-mips/translate.c | 1 + target-moxie/translate.c | 1 + target-openrisc/translate.c | 1 + target-ppc/translate.c | 1 + target-s390x/translate.c | 1 + target-sh4/translate.c | 1 + target-sparc/translate.c | 1 + target-tilegx/translate.c | 1 + target-tricore/translate.c | 1 + target-unicore32/translate.c | 1 + target-xtensa/translate.c | 1 + tcg/tcg.h | 4 ++++ translate-all.c | 2 ++ 21 files changed, 25 insertions(+) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 6154519..9395813 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -148,6 +148,7 @@ void alpha_translate_init(void) done_init =3D 1; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; =20 for (i =3D 0; i < 31; i++) { cpu_std_ir[i] =3D tcg_global_mem_new_i64(TCG_AREG0, diff --git a/target-arm/translate.c b/target-arm/translate.c index 7dc7862..61803ca 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -87,6 +87,7 @@ void arm_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; =20 for (i =3D 0; i < 16; i++) { cpu_R[i] =3D tcg_global_mem_new_i32(TCG_AREG0, diff --git a/target-cris/translate.c b/target-cris/translate.c index 9dd5c5f..576a5c6 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3355,6 +3355,7 @@ void cris_initialize_tcg(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; cc_x =3D tcg_global_mem_new(TCG_AREG0, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src =3D tcg_global_mem_new(TCG_AREG0, diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c index 3ab1c39..1ef8995 100644 --- a/target-cris/translate_v10.c +++ b/target-cris/translate_v10.c @@ -1249,6 +1249,7 @@ void cris_initialize_crisv10_tcg(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; cc_x =3D tcg_global_mem_new(TCG_AREG0, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src =3D tcg_global_mem_new(TCG_AREG0, diff --git a/target-i386/translate.c b/target-i386/translate.c index e191224..c304c87 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7818,6 +7818,7 @@ void optimize_flags_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; cpu_cc_op =3D tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUX86State, cc_op), "cc= _op"); cpu_cc_dst =3D tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, c= c_dst), diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 45abe53..a74847d 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1184,6 +1184,7 @@ void lm32_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; =20 for (i =3D 0; i < ARRAY_SIZE(cpu_R); i++) { cpu_R[i] =3D tcg_global_mem_new(TCG_AREG0, diff --git a/target-m68k/translate.c b/target-m68k/translate.c index e3ee9e0..a3f03b7 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -91,6 +91,7 @@ void m68k_tcg_init(void) "EXCEPTION"); =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; =20 p =3D cpu_reg_names; for (i =3D 0; i < 8; i++) { diff --git a/target-microblaze/translate.c b/target-microblaze/translate.= c index 6b0915e..2d73b64 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1862,6 +1862,7 @@ void mb_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; =20 env_debug =3D tcg_global_mem_new(TCG_AREG0,=20 offsetof(CPUMBState, debug), diff --git a/target-mips/translate.c b/target-mips/translate.c index 9ffb100..dc44458 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19783,6 +19783,7 @@ void mips_tcg_init(void) return; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; TCGV_UNUSED(cpu_gpr[0]); for (i =3D 1; i < 32; i++) cpu_gpr[i] =3D tcg_global_mem_new(TCG_AREG0, diff --git a/target-moxie/translate.c b/target-moxie/translate.c index f8c70cb..08acd07 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -109,6 +109,7 @@ void moxie_translate_init(void) return; } cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUMoxieState, pc), "$pc"); for (i =3D 0; i < 16; i++) diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index c122c20..7cb352f 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -77,6 +77,7 @@ void openrisc_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; cpu_sr =3D tcg_global_mem_new(TCG_AREG0, offsetof(CPUOpenRISCState, sr), "sr"); env_flags =3D tcg_global_mem_new_i32(TCG_AREG0, diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ff40c6b..78e763f 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -85,6 +85,7 @@ void ppc_translate_init(void) return; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; =20 p =3D cpu_reg_names; cpu_reg_names_size =3D sizeof(cpu_reg_names); diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 7e549d8..76f4cef 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -166,6 +166,7 @@ void s390x_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; psw_addr =3D tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, psw.addr), "psw_addr"); diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 7fb4900..5d6c1ec 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -98,6 +98,7 @@ void sh4_translate_init(void) return; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; =20 for (i =3D 0; i < 24; i++) cpu_gregs[i] =3D tcg_global_mem_new_i32(TCG_AREG0, diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 3d5d150..5bdf285 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5344,6 +5344,7 @@ void gen_intermediate_code_init(CPUSPARCState *env) inited =3D 1; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; cpu_regwptr =3D tcg_global_mem_new_ptr(TCG_AREG0, offsetof(CPUSPARCState, reg= wptr), "regwptr"); diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 0cd6700..23e4d1a 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -2434,6 +2434,7 @@ void tilegx_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUTLGState, p= c), "pc"); for (i =3D 0; i < TILEGX_R_COUNT; i++) { cpu_regs[i] =3D tcg_global_mem_new_i64(TCG_AREG0, diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 655db75..a56bf2c 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -8366,6 +8366,7 @@ void tricore_tcg_init(void) return; } cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; /* reg init */ for (i =3D 0 ; i < 16 ; i++) { cpu_gpr_a[i] =3D tcg_global_mem_new(TCG_AREG0, diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 6ba52c2..7d68232 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -72,6 +72,7 @@ void uc32_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; =20 for (i =3D 0; i < 32; i++) { cpu_R[i] =3D tcg_global_mem_new_i32(TCG_AREG0, diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index c6d7658..b4a00c1 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -217,6 +217,7 @@ void xtensa_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); + tcg_ctx.tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUXtensaState, pc), "pc"); =20 diff --git a/tcg/tcg.h b/tcg/tcg.h index 1585551..92d4604 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -572,6 +572,10 @@ struct TCGContext { =20 TBContext tb_ctx; =20 + /* Track vCPU triggering events */ + CPUState *cpu; /* *_trans */ + TCGv_cpu tcg_env; /* *_exec */ + /* The TCGBackendData structure is private to tcg-target.c. */ struct TCGBackendData *be; =20 diff --git a/translate-all.c b/translate-all.c index 5df7da5..5ae64d6 100644 --- a/translate-all.c +++ b/translate-all.c @@ -1203,6 +1203,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, ti =3D profile_getclock(); #endif =20 + tcg_ctx.cpu =3D ENV_GET_CPU(env); + tcg_func_start(&tcg_ctx); =20 gen_intermediate_code(env, tb);