From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZpKDm-00074K-He for qemu-devel@nongnu.org; Thu, 22 Oct 2015 14:04:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZpKDj-0005GC-BW for qemu-devel@nongnu.org; Thu, 22 Oct 2015 14:04:14 -0400 Received: from mail-qg0-x234.google.com ([2607:f8b0:400d:c04::234]:33942) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZpKDj-0005Fe-6h for qemu-devel@nongnu.org; Thu, 22 Oct 2015 14:04:11 -0400 Received: by qgem9 with SMTP id m9so63697272qge.1 for ; Thu, 22 Oct 2015 11:04:10 -0700 (PDT) Date: Thu, 22 Oct 2015 14:04:07 -0400 From: Kevin O'Connor Message-ID: <20151022180407.GA9969@morn.lan> References: <1445364840-7056-1-git-send-email-lersek@redhat.com> <20151021183625.26940.67906@jljusten-ivb> <5628A0E8.8050705@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5628A0E8.8050705@redhat.com> Subject: Re: [Qemu-devel] [PATCH] hw/isa/lpc_ich9: inject the SMI on the VCPU that is writing to APM_CNT List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: "Michael S. Tsirkin" , Jordan Justen , qemu-devel@nongnu.org, Gerd Hoffmann , Michael Kinney , Laszlo Ersek On Thu, Oct 22, 2015 at 10:40:08AM +0200, Paolo Bonzini wrote: > On 21/10/2015 20:36, Jordan Justen wrote: > > On 2015-10-20 11:14:00, Laszlo Ersek wrote: > > > Commit 4d00636e97b7 ("ich9: Add the lpc chip", Nov 14 2012) added the > > > ich9_apm_ctrl_changed() ioport write callback function such that it would > > > inject the SMI, in response to a write to the APM_CNT register, on the > > > first CPU, invariably. > > > > > > Since this register is used by guest code to trigger an SMI synchronously, > > > the interrupt should be injected on the VCPU that is performing the write. > > > > Why not send an SMI to *all* processors, like the real chipsets do? > > That's much less scalable, and more important I would have to check that > SeaBIOS can handle that correctly. It probably doesn't, as it doesn't > relocate SMBASEs. SeaBIOS is only expecting its SMI handler to be called once in response to a synchronous SMI. We can change SeaBIOS to fix that. SeaBIOS does relocate the smbase from 0x30000 to 0xa0000 during its init phase (by creating a synchronous SMI on the BSP and then setting the smbase register to 0xa0000 in the smi handler). -Kevin