From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zrx93-0002Iu-Gj for qemu-devel@nongnu.org; Thu, 29 Oct 2015 20:02:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zrx90-0005b5-BA for qemu-devel@nongnu.org; Thu, 29 Oct 2015 20:02:13 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:42051 helo=imgpgp01.kl.imgtec.org) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zrx90-0005at-2e for qemu-devel@nongnu.org; Thu, 29 Oct 2015 20:02:10 -0400 Date: Fri, 30 Oct 2015 00:02:07 +0000 From: James Hogan Message-ID: <20151030000207.GI5978@jhogan-linux.le.imgtec.org> References: <1445965957-37888-1-git-send-email-yongbok.kim@imgtec.com> <1445965957-37888-2-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="9sSKoi6Rw660DLir" Content-Disposition: inline In-Reply-To: <1445965957-37888-2-git-send-email-yongbok.kim@imgtec.com> Subject: Re: [Qemu-devel] [PATCH for-2.5 v2 1/4] target-mips: add CMGCRBase register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, crosthwaitepeter@gmail.com, pbonzini@redhat.com, leon.alrae@imgtec.com, aurelien@aurel32.net --9sSKoi6Rw660DLir Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Oct 27, 2015 at 05:12:34PM +0000, Yongbok Kim wrote: > Physical base address for the memory-mapped Coherency Manager Global > Configuration Register space. > The MIPS default location for the GCR_BASE address is 0x1FBF_8. > This register only exists if Config3 CMGCR is set to one. >=20 > Signed-off-by: Yongbok Kim > --- > target-mips/cpu.h | 3 ++- > target-mips/translate.c | 18 ++++++++++++++++++ > target-mips/translate_init.c | 3 ++- > 3 files changed, 22 insertions(+), 2 deletions(-) >=20 > diff --git a/target-mips/cpu.h b/target-mips/cpu.h > index c68681d..fdec7b7 100644 > --- a/target-mips/cpu.h > +++ b/target-mips/cpu.h > @@ -389,6 +389,7 @@ struct CPUMIPSState { > target_ulong CP0_EPC; > int32_t CP0_PRid; > int32_t CP0_EBase; > + target_ulong CP0_CMGCRBase; > int32_t CP0_Config0; > #define CP0C0_M 31 > #define CP0C0_K23 28 > @@ -431,7 +432,7 @@ struct CPUMIPSState { > int32_t CP0_Config3; > #define CP0C3_M 31 > #define CP0C3_BPG 30 > -#define CP0C3_CMCGR 29 > +#define CP0C3_CMGCR 29 > #define CP0C3_MSAP 28 > #define CP0C3_BP 27 > #define CP0C3_BI 26 > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 4cb77de..2f219fa 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -1426,6 +1426,7 @@ typedef struct DisasContext { > bool mvh; > int CP0_LLAddr_shift; > bool ps; > + bool cmgcr; > } DisasContext; > =20 > enum { > @@ -5273,6 +5274,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) > gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase)); > rn =3D "EBase"; > break; > + case 3: > + check_insn(ctx, ISA_MIPS32R2); > + CP0_CHECK(ctx->cmgcr); > + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCR= Base)); > + tcg_gen_ext32s_tl(arg, arg); > + rn =3D "CMGCRBase"; > + break; > default: > goto cp0_unimplemented; > } > @@ -6527,6 +6535,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg,= int reg, int sel) > gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase)); > rn =3D "EBase"; > break; > + case 3: > + check_insn(ctx, ISA_MIPS32R2); > + CP0_CHECK(ctx->cmgcr); > + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCR= Base)); > + rn =3D "CMGCRBase"; > + break; > default: > goto cp0_unimplemented; > } > @@ -19568,6 +19582,7 @@ void gen_intermediate_code(CPUMIPSState *env, str= uct TranslationBlock *tb) > ctx.ulri =3D (env->CP0_Config3 >> CP0C3_ULRI) & 1; > ctx.ps =3D ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || > (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); > + ctx.cmgcr =3D (env->CP0_Config3 >> CP0C3_CMGCR) & 1; > restore_cpu_state(env, &ctx); > #ifdef CONFIG_USER_ONLY > ctx.mem_idx =3D MIPS_HFLAG_UM; > @@ -19956,6 +19971,9 @@ void cpu_state_reset(CPUMIPSState *env) > } else { > env->CP0_EBase |=3D 0x80000000; > } > + if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { > + env->CP0_CMGCRBase =3D 0x1fbf8000 >> 4; This is technically hardware configurable, but I'm guessing we can worry about emulation of platforms that set it to something different later. > + } > env->CP0_Status =3D (1 << CP0St_BEV) | (1 << CP0St_ERL); > /* vectored interrupts not implemented, timer on int 7, > no performance counters. */ > diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c > index 1b45884..a6b8986 100644 > --- a/target-mips/translate_init.c > +++ b/target-mips/translate_init.c > @@ -660,7 +660,8 @@ static const mips_def_t mips_defs[] =3D > (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_D= A) | > (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_E= P), > .CP0_Config2 =3D MIPS_CONFIG2, > - .CP0_Config3 =3D MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MS= AP) | > + .CP0_Config3 =3D MIPS_CONFIG3 | (1U << CP0C3_M) | > + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | You're enabling the bit to tell the guest that the CMGCRs are present, but they're not yet, only the cop0 registers. Perhaps this hunk of the patch should come after those memory mapped registers are implemented, so as not to break bisection. Otherwise: Reviewed-by: James Hogan Cheers James > (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_U= LRI) | > (1 << CP0C3_RXI) | (1 << CP0C3_LPA), > .CP0_Config4 =3D MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE= ) | > --=20 > 1.7.1 >=20 --9sSKoi6Rw660DLir Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJWMrN/AAoJEGwLaZPeOHZ6Ij8P/3eUxwywdDDKpnWTTTbALQhS +jYF2eZO23DRB9bLTKuhpmr6p/A5qktzvfF7u97nwBxPDinGaeuniwg3hp8W98cZ hi+zdziDGHrWj+6FX7Ds5bSeYvrWNjaF3Ky0z7vxtcwCtSMhMvNQYorlJMcSHeLM H1esPMgwI1HFgnA4gp3bAdEpJMkbAuh+73o9t/hgyqT8Qbvn/ERFPIKvOogmlfjG rm2jWVAWKQZKgfxI4Gs9VYglIpgRwLmkcZ2JkSuSglhP5tMmJ0CO497GcFvp7DN1 p3BTtrP/Wijs/PHNZy+bRxec1poA9xdrhcf8/lkeAlA74FNomelh4bwqdpmS0ApZ SUy6GZPFrA2BE0AfBwrdaoW9cSvXebh+eWEJzhB5BqxYWlSWDk55LjflCDiSlbsw ngbrTyFsEPGExhnKoHVZ8IwZiyQZoF4VmlmM4AyCHq4UUdWDAxmi9JPBa2xbq5yD abIyW8f20zzfUROqgYc07ZoX3awEDM5Frn1l/AE5vtnk68oiwcy8be3hHYwnkb9s ThBrfBGhm1Bue3OoeobU21VH8HksPbuFrxpwKLG1jRtvUkF1T5k+74dDGFu65OJh jxTCtOCwqaCkelsZ8bOfv7uLe7Kd+dEFjWaGm/95TiomPVVrPsfqg3VEuWuUxTtZ JNdIUw9AwqBGHqyCaTMs =u54U -----END PGP SIGNATURE----- --9sSKoi6Rw660DLir--