From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52644) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zrxfy-0007A3-7i for qemu-devel@nongnu.org; Thu, 29 Oct 2015 20:36:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zrxfu-0005Xt-3w for qemu-devel@nongnu.org; Thu, 29 Oct 2015 20:36:14 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:3233 helo=imgpgp01.kl.imgtec.org) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zrxft-0005Xk-Lt for qemu-devel@nongnu.org; Thu, 29 Oct 2015 20:36:10 -0400 Date: Fri, 30 Oct 2015 00:36:07 +0000 From: James Hogan Message-ID: <20151030003607.GJ5978@jhogan-linux.le.imgtec.org> References: <1445965957-37888-1-git-send-email-yongbok.kim@imgtec.com> <1445965957-37888-3-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="HkMjoL2LAeBLhbFV" Content-Disposition: inline In-Reply-To: <1445965957-37888-3-git-send-email-yongbok.kim@imgtec.com> Subject: Re: [Qemu-devel] [PATCH for-2.5 v2 2/4] mips: add Global Config Register block (part) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, crosthwaitepeter@gmail.com, pbonzini@redhat.com, leon.alrae@imgtec.com, aurelien@aurel32.net --HkMjoL2LAeBLhbFV Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Yongbok, On Tue, Oct 27, 2015 at 05:12:35PM +0000, Yongbok Kim wrote: > Add part of GCR Block which Linux Kernel utilises and it is enough > to bring the GIC up. > It defines full 32 Kbytes address space allocated for GCR but only few > registers are implemented such as config, revision, status, L2 config and > local config registers. > To support MIPS Coherent Manager, this module would be necessary to be ex= tended s/Coherent/Coherence/ > further. >=20 > Signed-off-by: Yongbok Kim > --- > default-configs/mips-softmmu.mak | 1 + > default-configs/mips64-softmmu.mak | 1 + > default-configs/mips64el-softmmu.mak | 1 + > default-configs/mipsel-softmmu.mak | 1 + > hw/misc/Makefile.objs | 1 + > hw/misc/mips_gcr.c | 113 ++++++++++++++++++++++++++++= ++++++ > include/hw/misc/mips_gcr.h | 58 +++++++++++++++++ would these be better named mips_cmgcr.{h,c}? > 7 files changed, 176 insertions(+), 0 deletions(-) > create mode 100644 hw/misc/mips_gcr.c > create mode 100644 include/hw/misc/mips_gcr.h >=20 > diff --git a/default-configs/mips-softmmu.mak b/default-configs/mips-soft= mmu.mak > index 44467c3..a784644 100644 > --- a/default-configs/mips-softmmu.mak > +++ b/default-configs/mips-softmmu.mak > @@ -30,3 +30,4 @@ CONFIG_I8259=3Dy > CONFIG_MC146818RTC=3Dy > CONFIG_ISA_TESTDEV=3Dy > CONFIG_EMPTY_SLOT=3Dy > +CONFIG_MIPS_GIC=3Dy > diff --git a/default-configs/mips64-softmmu.mak b/default-configs/mips64-= softmmu.mak > index 66ed5f9..957508d 100644 > --- a/default-configs/mips64-softmmu.mak > +++ b/default-configs/mips64-softmmu.mak > @@ -36,3 +36,4 @@ CONFIG_JAZZ_LED=3Dy > CONFIG_MC146818RTC=3Dy > CONFIG_ISA_TESTDEV=3Dy > CONFIG_EMPTY_SLOT=3Dy > +CONFIG_MIPS_GIC=3Dy > diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips6= 4el-softmmu.mak > index bfca2b2..6c1065f 100644 > --- a/default-configs/mips64el-softmmu.mak > +++ b/default-configs/mips64el-softmmu.mak > @@ -39,3 +39,4 @@ CONFIG_MC146818RTC=3Dy > CONFIG_VT82C686=3Dy > CONFIG_ISA_TESTDEV=3Dy > CONFIG_EMPTY_SLOT=3Dy > +CONFIG_MIPS_GIC=3Dy > diff --git a/default-configs/mipsel-softmmu.mak b/default-configs/mipsel-= softmmu.mak > index 0162ef0..4633b0b 100644 > --- a/default-configs/mipsel-softmmu.mak > +++ b/default-configs/mipsel-softmmu.mak > @@ -30,3 +30,4 @@ CONFIG_I8259=3Dy > CONFIG_MC146818RTC=3Dy > CONFIG_ISA_TESTDEV=3Dy > CONFIG_EMPTY_SLOT=3Dy > +CONFIG_MIPS_GIC=3Dy > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs > index 4aa76ff..02ac5bb 100644 > --- a/hw/misc/Makefile.objs > +++ b/hw/misc/Makefile.objs > @@ -37,6 +37,7 @@ obj-$(CONFIG_OMAP) +=3D omap_tap.o > obj-$(CONFIG_SLAVIO) +=3D slavio_misc.o > obj-$(CONFIG_ZYNQ) +=3D zynq_slcr.o > obj-$(CONFIG_STM32F2XX_SYSCFG) +=3D stm32f2xx_syscfg.o > +obj-$(CONFIG_MIPS_GIC) +=3D mips_gcr.o would CONFIG_MIPS_CMGCR be a better name? > =20 > obj-$(CONFIG_PVPANIC) +=3D pvpanic.o > obj-$(CONFIG_EDU) +=3D edu.o > diff --git a/hw/misc/mips_gcr.c b/hw/misc/mips_gcr.c > new file mode 100644 > index 0000000..6db4a9d > --- /dev/null > +++ b/hw/misc/mips_gcr.c > @@ -0,0 +1,113 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General P= ublic > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. > + * Authors: Sanjay Lal > + * > + * Copyright (C) 2015 Imagination Technologies > + */ > + > +#include "hw/hw.h" > +#include "hw/sysbus.h" > +#include "sysemu/sysemu.h" > +#include "hw/misc/mips_gcr.h" > +#include "hw/intc/mips_gic.h" I don't think this header exists yet at this point in the patchset. > + > +/* Read GCR registers */ > +static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size) > +{ > + MIPSGCRState *gcr =3D (MIPSGCRState *) opaque; > + > + switch (addr) { > + /* Global Control Block Register */ > + case GCR_CONFIG_OFS: > + /* Set PCORES to 0 */ > + return 0; > + case GCR_BASE_OFS: > + return gcr->gcr_base; > + case GCR_REV_OFS: > + return gcr->gcr_rev; > + case GCR_GIC_BASE_OFS: > + return gcr->gic_base; > + case GCR_GIC_STATUS_OFS: > + return GCR_GIC_STATUS_GICEX_MSK; well, it doesn't exist yet, does it? > + case GCR_CPC_STATUS_OFS: > + return 0; > + case GCR_L2_CONFIG_OFS: > + /* L2 BYPASS */ > + return GCR_L2_CONFIG_BYPASS_MSK; > + /* Core-Local and Core-Other Control Blocks */ > + case MIPS_CLCB_OFS + GCR_CL_CONFIG_OFS: > + case MIPS_COCB_OFS + GCR_CL_CONFIG_OFS: > + /* Set PVP to # cores - 1 */ > + return gcr->num_vps - 1; > + case MIPS_CLCB_OFS + GCR_CL_OTHER_OFS: > + return 0; > + default: > + qemu_log_mask(LOG_UNIMP, "Read %d bytes at GCR offset 0x%" PRIx6= 4 "\n", > + size, addr); > + return 0; > + } > + return 0; > +} > + > +/* Write GCR registers */ > +static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned= size) > +{ > + switch (addr) { > + default: > + qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" PRIx= 64 > + " 0x%08lx\n", size, addr, data); > + break; > + } > +} > + > +static const MemoryRegionOps gcr_ops =3D { > + .read =3D gcr_read, > + .write =3D gcr_write, > + .endianness =3D DEVICE_NATIVE_ENDIAN, > + .impl =3D { > + .max_access_size =3D 8, > + }, > +}; > + > +static void mips_gcr_init(Object *obj) > +{ > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); > + MIPSGCRState *s =3D MIPS_GCR(obj); > + > + memory_region_init_io(&s->iomem, OBJECT(s), &gcr_ops, s, > + "mips-gcr", GCR_ADDRSPACE_SZ); > + sysbus_init_mmio(sbd, &s->iomem); > +} > + > +static Property mips_gcr_properties[] =3D { > + DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1), > + DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800), Is this configurable per core? > + DEFINE_PROP_UINT64("gcr-base", MIPSGCRState, gcr_base, GCR_BASE_ADDR= ), > + DEFINE_PROP_UINT64("gic-base", MIPSGCRState, gic_base, GIC_BASE_ADDR= ), GIC_BASE_ADDR is not defined yet. Maybe this should be added in a later patch. > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void mips_gcr_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(klass); > + dc->props =3D mips_gcr_properties; > +} > + > +static const TypeInfo mips_gcr_info =3D { > + .name =3D TYPE_MIPS_GCR, > + .parent =3D TYPE_SYS_BUS_DEVICE, > + .instance_size =3D sizeof(MIPSGCRState), > + .instance_init =3D mips_gcr_init, > + .class_init =3D mips_gcr_class_init, > +}; > + > +static void mips_gcr_register_types(void) > +{ > + type_register_static(&mips_gcr_info); > +} > + > +type_init(mips_gcr_register_types) > diff --git a/include/hw/misc/mips_gcr.h b/include/hw/misc/mips_gcr.h > new file mode 100644 > index 0000000..28f3ca7 > --- /dev/null > +++ b/include/hw/misc/mips_gcr.h > @@ -0,0 +1,58 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General P= ublic > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2015 Imagination Technologies > + * > + */ > + > +#ifndef _MIPS_GCR_H > +#define _MIPS_GCR_H > + > +#define TYPE_MIPS_GCR "mips-gcr" > +#define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR) > + > +#define GCR_BASE_ADDR 0x1fbf8000ULL > +#define GCR_ADDRSPACE_SZ 0x8000 > + > +/* Offsets to register blocks */ > +#define MIPS_GCB_OFS 0x0000 /* Global Control Block */ > +#define MIPS_CLCB_OFS 0x2000 /* Core Local Control Block */ > +#define MIPS_COCB_OFS 0x4000 /* Core Other Control Block */ > +#define MIPS_GDB_OFS 0x6000 /* Global Debug Block */ > + > +/* Global Control Block Register Map */ > +#define GCR_CONFIG_OFS 0x0000 > +#define GCR_BASE_OFS 0x0008 Since QEMU supports XPA, perhaps we should have GCR_BASE_UPPER implemented too (like P5600). > +#define GCR_REV_OFS 0x0030 > +#define GCR_GIC_BASE_OFS 0x0080 Same, GIC_BASE_UPPER? > +#define GCR_GIC_STATUS_OFS 0x00D0 > +#define GCR_CPC_STATUS_OFS 0x00F0 > +#define GCR_L2_CONFIG_OFS 0x0130 > + > +/* Core Local and Core Other Block Register Map */ > +#define GCR_CL_CONFIG_OFS 0x0010 > +#define GCR_CL_OTHER_OFS 0x0018 > + > +/* GCR_GIC_STATUS register fields */ > +#define GCR_GIC_STATUS_GICEX_SHF 0 > +#define GCR_GIC_STATUS_GICEX_MSK ((0x1ULL) << GCR_GIC_STATUS_GICEX_SH= F) > + > +/* GCR_L2_CONFIG register fields */ > +#define GCR_L2_CONFIG_BYPASS_SHF 20 > +#define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SH= F) > + > + > +typedef struct MIPSGCRState MIPSGCRState; > +struct MIPSGCRState { > + SysBusDevice parent_obj; > + > + int32_t gcr_rev; > + int32_t num_vps; > + hwaddr gcr_base; > + hwaddr gic_base; > + MemoryRegion iomem; > +} ; unneeded whitespace before ";" Cheers James > + > +#endif /* _MIPS_GCR_H */ > --=20 > 1.7.1 >=20 --HkMjoL2LAeBLhbFV Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJWMrt3AAoJEGwLaZPeOHZ6f7IP/1uwZM7xLYC813TDpxCKflBT dZAwlrFJB9T60f4FdFINgjAVycUGoOuxWJvKHAEgc7uGkocGuAJdEPFb30LOyMVJ +Mu1ACyZ04bg7EBCOJ8jq4Us0j2rEigRjcIqNvwFtXoetCQ+C/1LYzxMeFSIHx4Z VUZnI11E3k+MMiA2U6s0QOvNj1+zNYmWQl8iqoWbrSC6ndLhFHaah55/kkN+q+D5 bRY2d71zaByWyGWYQt51SKAtwS+0KgLwTuYo+5zhJ+415u6J3ZmQ/mpiUlGLnu8w /BMSErT1yJ0F7HgE2QUaLaiC0sldxhKU/fkkmmQujOflB5FG7XkoVJRZRgWq9U6i hVmImtWM5cMf7zVtIwQcUdCSm6F0o2Ox69n8uGBl8+bOgg5MpZcbpQNdOCQMPhau axXX5vufzbC4vDJNT3d8Rjm3pN9x/FZ6b7K26GmjAqthPJzL8vIqsxp8gVFG94pk Sx20DWDFXj+7+Ht5n2D6y/8swi13g10MGkRIIamaecxAgalbp3cChrPK426nh6Jt 0o8XnG1uhe2VlK+kJfe7+hYyuBsSqgCvO63rUX0ZQfyOUqKqpUN8Q84DKU1Ektnn L24ch1z3fx9bWu+8NTqFZGGPerSFR0929m01Qs73fOwY/LDpH+vDnVTct+aUu6sQ LbCxi1w9lcXm/kiK2bfB =6xQR -----END PGP SIGNATURE----- --HkMjoL2LAeBLhbFV--