From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57224) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZtozH-0004Nc-OG for qemu-devel@nongnu.org; Tue, 03 Nov 2015 22:43:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZtozF-0002Pp-4n for qemu-devel@nongnu.org; Tue, 03 Nov 2015 22:43:51 -0500 Date: Wed, 4 Nov 2015 14:19:26 +1100 From: David Gibson Message-ID: <20151104031926.GI21954@voom.redhat.com> References: <1445608598-24485-1-git-send-email-mark.cave-ayland@ilande.co.uk> <1445608598-24485-10-git-send-email-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="MFZs98Tklfu0WsCO" Content-Disposition: inline In-Reply-To: <1445608598-24485-10-git-send-email-mark.cave-ayland@ilande.co.uk> Subject: Re: [Qemu-devel] [PATCH 09/13] cuda.c: add defines for CUDA registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Cave-Ayland Cc: cormac@c-obrien.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, agraf@suse.de --MFZs98Tklfu0WsCO Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Oct 23, 2015 at 02:56:34PM +0100, Mark Cave-Ayland wrote: > Signed-off-by: Mark Cave-Ayland Reviewed-by: David Gibson > --- > hw/misc/macio/cuda.c | 87 ++++++++++++++++++++++++++++++--------------= ------ > 1 file changed, 53 insertions(+), 34 deletions(-) >=20 > diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c > index 4027713..d32afc6 100644 > --- a/hw/misc/macio/cuda.c > +++ b/hw/misc/macio/cuda.c > @@ -110,6 +110,24 @@ > /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */ > #define RTC_OFFSET 2082844800 > =20 > +/* CUDA registers */ > +#define CUDA_REG_B 0x00 > +#define CUDA_REG_A 0x01 > +#define CUDA_REG_DIRB 0x02 > +#define CUDA_REG_DIRA 0x03 > +#define CUDA_REG_T1CL 0x04 > +#define CUDA_REG_T1CH 0x05 > +#define CUDA_REG_T1LL 0x06 > +#define CUDA_REG_T1LH 0x07 > +#define CUDA_REG_T2CL 0x08 > +#define CUDA_REG_T2CH 0x09 > +#define CUDA_REG_SR 0x0a > +#define CUDA_REG_ACR 0x0b > +#define CUDA_REG_PCR 0x0c > +#define CUDA_REG_IFR 0x0d > +#define CUDA_REG_IER 0x0e > +#define CUDA_REG_ANH 0x0f > + > static void cuda_update(CUDAState *s); > static void cuda_receive_packet_from_host(CUDAState *s, > const uint8_t *data, int len); > @@ -226,66 +244,67 @@ static uint32_t cuda_readb(void *opaque, hwaddr add= r) > =20 > addr =3D (addr >> 9) & 0xf; > switch(addr) { > - case 0: > + case CUDA_REG_B: > val =3D s->b; > break; > - case 1: > + case CUDA_REG_A: > val =3D s->a; > break; > - case 2: > + case CUDA_REG_DIRB: > val =3D s->dirb; > break; > - case 3: > + case CUDA_REG_DIRA: > val =3D s->dira; > break; > - case 4: > + case CUDA_REG_T1CL: > val =3D get_counter(&s->timers[0]) & 0xff; > s->ifr &=3D ~T1_INT; > cuda_update_irq(s); > break; > - case 5: > + case CUDA_REG_T1CH: > val =3D get_counter(&s->timers[0]) >> 8; > cuda_update_irq(s); > break; > - case 6: > + case CUDA_REG_T1LL: > val =3D s->timers[0].latch & 0xff; > break; > - case 7: > + case CUDA_REG_T1LH: > /* XXX: check this */ > val =3D (s->timers[0].latch >> 8) & 0xff; > break; > - case 8: > + case CUDA_REG_T2CL: > val =3D get_counter(&s->timers[1]) & 0xff; > s->ifr &=3D ~T2_INT; > break; > - case 9: > + case CUDA_REG_T2CH: > val =3D get_counter(&s->timers[1]) >> 8; > break; > - case 10: > + case CUDA_REG_SR: > val =3D s->sr; > s->ifr &=3D ~(SR_INT | SR_CLOCK_INT | SR_DATA_INT); > cuda_update_irq(s); > break; > - case 11: > + case CUDA_REG_ACR: > val =3D s->acr; > break; > - case 12: > + case CUDA_REG_PCR: > val =3D s->pcr; > break; > - case 13: > + case CUDA_REG_IFR: > val =3D s->ifr; > - if (s->ifr & s->ier) > + if (s->ifr & s->ier) { > val |=3D 0x80; > + } > break; > - case 14: > + case CUDA_REG_IER: > val =3D s->ier | 0x80; > break; > default: > - case 15: > + case CUDA_REG_ANH: > val =3D s->anh; > break; > } > - if (addr !=3D 13 || val !=3D 0) { > + if (addr !=3D CUDA_REG_IFR || val !=3D 0) { > CUDA_DPRINTF("read: reg=3D0x%x val=3D%02x\n", (int)addr, val); > } > =20 > @@ -300,61 +319,61 @@ static void cuda_writeb(void *opaque, hwaddr addr, = uint32_t val) > CUDA_DPRINTF("write: reg=3D0x%x val=3D%02x\n", (int)addr, val); > =20 > switch(addr) { > - case 0: > + case CUDA_REG_B: > s->b =3D val; > cuda_update(s); > break; > - case 1: > + case CUDA_REG_A: > s->a =3D val; > break; > - case 2: > + case CUDA_REG_DIRB: > s->dirb =3D val; > break; > - case 3: > + case CUDA_REG_DIRA: > s->dira =3D val; > break; > - case 4: > + case CUDA_REG_T1CL: > s->timers[0].latch =3D (s->timers[0].latch & 0xff00) | val; > cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK= _VIRTUAL)); > break; > - case 5: > + case CUDA_REG_T1CH: > s->timers[0].latch =3D (s->timers[0].latch & 0xff) | (val << 8); > s->ifr &=3D ~T1_INT; > set_counter(s, &s->timers[0], s->timers[0].latch); > break; > - case 6: > + case CUDA_REG_T1LL: > s->timers[0].latch =3D (s->timers[0].latch & 0xff00) | val; > cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK= _VIRTUAL)); > break; > - case 7: > + case CUDA_REG_T1LH: > s->timers[0].latch =3D (s->timers[0].latch & 0xff) | (val << 8); > s->ifr &=3D ~T1_INT; > cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK= _VIRTUAL)); > break; > - case 8: > + case CUDA_REG_T2CL: > s->timers[1].latch =3D val; > set_counter(s, &s->timers[1], val); > break; > - case 9: > + case CUDA_REG_T2CH: > set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch); > break; > - case 10: > + case CUDA_REG_SR: > s->sr =3D val; > break; > - case 11: > + case CUDA_REG_ACR: > s->acr =3D val; > cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK= _VIRTUAL)); > cuda_update(s); > break; > - case 12: > + case CUDA_REG_PCR: > s->pcr =3D val; > break; > - case 13: > + case CUDA_REG_IFR: > /* reset bits */ > s->ifr &=3D ~val; > cuda_update_irq(s); > break; > - case 14: > + case CUDA_REG_IER: > if (val & IER_SET) { > /* set bits */ > s->ier |=3D val & 0x7f; > @@ -365,7 +384,7 @@ static void cuda_writeb(void *opaque, hwaddr addr, ui= nt32_t val) > cuda_update_irq(s); > break; > default: > - case 15: > + case CUDA_REG_ANH: > s->anh =3D val; > break; > } --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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