From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57220) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZtozH-0004NX-NK for qemu-devel@nongnu.org; Tue, 03 Nov 2015 22:43:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZtozF-0002Py-5c for qemu-devel@nongnu.org; Tue, 03 Nov 2015 22:43:51 -0500 Date: Wed, 4 Nov 2015 14:40:29 +1100 From: David Gibson Message-ID: <20151104034029.GL21954@voom.redhat.com> References: <1445608598-24485-1-git-send-email-mark.cave-ayland@ilande.co.uk> <1445608598-24485-13-git-send-email-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="DXIF1lRUlMsbZ3S1" Content-Disposition: inline In-Reply-To: <1445608598-24485-13-git-send-email-mark.cave-ayland@ilande.co.uk> Subject: Re: [Qemu-devel] [PATCH 12/13] cuda.c: fix T2 timer and enable its interrupt List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Cave-Ayland Cc: cormac@c-obrien.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, agraf@suse.de --DXIF1lRUlMsbZ3S1 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Oct 23, 2015 at 02:56:37PM +0100, Mark Cave-Ayland wrote: > Fix the counter loading logic and enable the T2 interrupt when the timer > expires. A mention of what uses T2, and therefore why this is useful would be good. >=20 > Signed-off-by: Mark Cave-Ayland > --- > hw/misc/macio/cuda.c | 30 +++++++++++++++++++++--------- > 1 file changed, 21 insertions(+), 9 deletions(-) >=20 > diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c > index 687cb54..d864b24 100644 > --- a/hw/misc/macio/cuda.c > +++ b/hw/misc/macio/cuda.c > @@ -136,7 +136,7 @@ static void cuda_timer_update(CUDAState *s, CUDATimer= *ti, > =20 > static void cuda_update_irq(CUDAState *s) > { > - if (s->ifr & s->ier & (SR_INT | T1_INT)) { > + if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) { > qemu_irq_raise(s->irq); > } else { > qemu_irq_lower(s->irq); > @@ -175,7 +175,7 @@ static unsigned int get_counter(CUDATimer *ti) > =20 > static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) > { > - CUDA_DPRINTF("T%d.counter=3D%d\n", 1 + (ti->timer =3D=3D NULL), val); > + CUDA_DPRINTF("T%d.counter=3D%d\n", 1 + ti->index, val); > ti->load_time =3D get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), > s->frequency); > ti->counter_value =3D val; > @@ -220,7 +220,7 @@ static void cuda_timer_update(CUDAState *s, CUDATimer= *ti, > { > if (!ti->timer) > return; > - if ((s->acr & T1MODE) !=3D T1MODE_CONT) { > + if (ti->index =3D=3D 0 && (s->acr & T1MODE) !=3D T1MODE_CONT) { > timer_del(ti->timer); > } else { > ti->next_irq_time =3D get_next_irq_time(ti, current_time); > @@ -238,6 +238,16 @@ static void cuda_timer1(void *opaque) > cuda_update_irq(s); > } > =20 > +static void cuda_timer2(void *opaque) > +{ > + CUDAState *s =3D opaque; > + CUDATimer *ti =3D &s->timers[1]; > + > + cuda_timer_update(s, ti, ti->next_irq_time); > + s->ifr |=3D T2_INT; > + cuda_update_irq(s); > +} > + > static uint32_t cuda_readb(void *opaque, hwaddr addr) > { > CUDAState *s =3D opaque; > @@ -276,6 +286,7 @@ static uint32_t cuda_readb(void *opaque, hwaddr addr) > case CUDA_REG_T2CL: > val =3D get_counter(&s->timers[1]) & 0xff; > s->ifr &=3D ~T2_INT; > + cuda_update_irq(s); > break; > case CUDA_REG_T2CH: > val =3D get_counter(&s->timers[1]) >> 8; > @@ -352,11 +363,12 @@ static void cuda_writeb(void *opaque, hwaddr addr, = uint32_t val) > cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK= _VIRTUAL)); > break; > case CUDA_REG_T2CL: > - s->timers[1].latch =3D val; > - set_counter(s, &s->timers[1], val); > + s->timers[1].latch =3D (s->timers[1].latch & 0xff00) | val; > break; > case CUDA_REG_T2CH: > - set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch); > + s->timers[1].latch =3D (s->timers[1].latch & 0xff) | (val << 8); > + s->ifr &=3D ~T2_INT; > + set_counter(s, &s->timers[1], s->timers[1].latch); So the new code appears to be like that for T1CL / T1CH, which makes sense. However, T1CL has a cuda_timer_update() call. Do you also need that for T2CL? > break; > case CUDA_REG_SR: > s->sr =3D val; > @@ -719,8 +731,7 @@ static void cuda_reset(DeviceState *dev) > s->timers[0].latch =3D 0xffff; > set_counter(s, &s->timers[0], 0xffff); > =20 > - s->timers[1].latch =3D 0; > - set_counter(s, &s->timers[1], 0xffff); > + s->timers[1].latch =3D 0xffff; > } > =20 > static void cuda_realizefn(DeviceState *dev, Error **errp) > @@ -730,7 +741,8 @@ static void cuda_realizefn(DeviceState *dev, Error **= errp) > =20 > s->timers[0].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1,= s); > s->timers[0].frequency =3D s->frequency; > - s->timers[1].frequency =3D s->frequency; > + s->timers[1].timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer2,= s); > + s->timers[1].frequency =3D (SCALE_US * 6000) / 4700; Where does this T2 frequency come from? > qemu_get_timedate(&tm, 0); > s->tick_offset =3D (uint32_t)mktimegm(&tm) + RTC_OFFSET; --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --DXIF1lRUlMsbZ3S1 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWOX4tAAoJEGw4ysog2bOSAO8QANSwS+wqolzvGjgar6hwHddY BIIF1rcehZDPmY5yw0rnv7YJkwVeSWMKYhLUPqZqcHNWuc9NZAa4gPdDTYn9QZ3b pD/ZYEYlijdcKcPETU7VenEeYX+ekDz97Kp5tuECmb5zunvDa8U2Y1n0TqjOIR0d p9XEjgkBIoMsQrT9NfkY8V0mEHNHeeYAPzQ682kjqPWTA79pKADy6PhYebLH6aMQ xy6CJES1pHszxO1ppxxu0BvaOVPfoM+k0ww55j09YrXKbhoqDwbpUT84/aVveP3Z f6b+6DCQB48tTzdAPSkUVpIckAu8lKQzW/0WilUCZ14J5b3g5yikPfehjRTOUaLE q7iG6wMWcLKgNreL+trSVlG0g2NW8cg3g73kbSO8QqoZGN7CYQ4PBlt1FTdMMjKR pDowDwK9SqCiB1XPSlPnUPfMZFlfaDIwxkEMPaH4VGnue51AMuwmRgiha0NbDX+9 B8yxB81LRtdMUsABtgJ7CVHUyqQreqJH0/xJNlzED6o6sbFL39hKNwToFAAQEZPK GwNSmo9zroneV45xWK/IgWNb/QCHM2gGR+8+2eNLBKJ13LMbu858HoBve3eSASGj kKovbUzpgssjeXH8zBOb3jBP7JLzcNREpTA1oIZympT81JlCEyTXhpHoMKMz32Rs HYfFZjdJa+SJvuZGtb9s =ZXK/ -----END PGP SIGNATURE----- --DXIF1lRUlMsbZ3S1--