From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48835) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZwYjT-0002yL-MX for qemu-devel@nongnu.org; Wed, 11 Nov 2015 11:59:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZwYge-00037l-AA for qemu-devel@nongnu.org; Wed, 11 Nov 2015 11:58:51 -0500 Received: from mx1.redhat.com ([209.132.183.28]:59749) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZwYge-00037e-2P for qemu-devel@nongnu.org; Wed, 11 Nov 2015 11:55:56 -0500 Date: Wed, 11 Nov 2015 18:55:52 +0200 From: "Michael S. Tsirkin" Message-ID: <20151111185547-mutt-send-email-mst@redhat.com> References: <70e2840f31bce7610a2b04a3390589b3085035b3.1447231392.git.chen.fan.fnst@cn.fujitsu.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <70e2840f31bce7610a2b04a3390589b3085035b3.1447231392.git.chen.fan.fnst@cn.fujitsu.com> Subject: Re: [Qemu-devel] [PATCH v13 06/13] aer: impove pcie_aer_init to support vfio device List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Cao jin Cc: Chen Fan , alex.williamson@redhat.com, qemu-devel@nongnu.org On Wed, Nov 11, 2015 at 06:34:24PM +0800, Cao jin wrote: > From: Chen Fan > > pcie_aer_init was used to emulate an aer capability for pcie device, > but for vfio device, the aer config space size is mutable and is not > always equal to PCI_ERR_SIZEOF(0x48). it depends on where the TLP Prefix > register required, so here we add a size argument. > > Signed-off-by: Chen Fan Reviewed-by: Michael S. Tsirkin > --- > hw/pci-bridge/ioh3420.c | 2 +- > hw/pci-bridge/xio3130_downstream.c | 2 +- > hw/pci-bridge/xio3130_upstream.c | 2 +- > hw/pci/pcie_aer.c | 4 ++-- > include/hw/pci/pcie_aer.h | 2 +- > 5 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c > index cce2fdd..4d9cd3f 100644 > --- a/hw/pci-bridge/ioh3420.c > +++ b/hw/pci-bridge/ioh3420.c > @@ -129,7 +129,7 @@ static int ioh3420_initfn(PCIDevice *d) > goto err_pcie_cap; > } > pcie_cap_root_init(d); > - rc = pcie_aer_init(d, IOH_EP_AER_OFFSET); > + rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF); > if (rc < 0) { > goto err; > } > diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c > index b3a6479..9737041 100644 > --- a/hw/pci-bridge/xio3130_downstream.c > +++ b/hw/pci-bridge/xio3130_downstream.c > @@ -92,7 +92,7 @@ static int xio3130_downstream_initfn(PCIDevice *d) > goto err_pcie_cap; > } > pcie_cap_arifwd_init(d); > - rc = pcie_aer_init(d, XIO3130_AER_OFFSET); > + rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); > if (rc < 0) { > goto err; > } > diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c > index eada582..4d7f894 100644 > --- a/hw/pci-bridge/xio3130_upstream.c > +++ b/hw/pci-bridge/xio3130_upstream.c > @@ -81,7 +81,7 @@ static int xio3130_upstream_initfn(PCIDevice *d) > } > pcie_cap_flr_init(d); > pcie_cap_deverr_init(d); > - rc = pcie_aer_init(d, XIO3130_AER_OFFSET); > + rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); > if (rc < 0) { > goto err; > } > diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c > index 98d2c18..45f351b 100644 > --- a/hw/pci/pcie_aer.c > +++ b/hw/pci/pcie_aer.c > @@ -94,12 +94,12 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log) > aer_log->log_num = 0; > } > > -int pcie_aer_init(PCIDevice *dev, uint16_t offset) > +int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size) > { > PCIExpressDevice *exp; > > pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER, > - offset, PCI_ERR_SIZEOF); > + offset, size); > exp = &dev->exp; > exp->aer_cap = offset; > > diff --git a/include/hw/pci/pcie_aer.h b/include/hw/pci/pcie_aer.h > index 2fb8388..156acb0 100644 > --- a/include/hw/pci/pcie_aer.h > +++ b/include/hw/pci/pcie_aer.h > @@ -87,7 +87,7 @@ struct PCIEAERErr { > > extern const VMStateDescription vmstate_pcie_aer_log; > > -int pcie_aer_init(PCIDevice *dev, uint16_t offset); > +int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size); > void pcie_aer_exit(PCIDevice *dev); > void pcie_aer_write_config(PCIDevice *dev, > uint32_t addr, uint32_t val, int len); > -- > 1.9.3