From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45983) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zx5b1-0001px-Ah for qemu-devel@nongnu.org; Thu, 12 Nov 2015 23:04:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zx5ay-0003QR-3T for qemu-devel@nongnu.org; Thu, 12 Nov 2015 23:04:19 -0500 Date: Fri, 13 Nov 2015 12:58:16 +1100 From: David Gibson Message-ID: <20151113015816.GK4886@voom.redhat.com> References: <20151111171135.4328.41819.stgit@aravindap> <20151111171602.4328.34006.stgit@aravindap> <56444957.9080003@redhat.com> <5644D931.1070407@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="fLj60tP2PZ34xyqD" Content-Disposition: inline In-Reply-To: <5644D931.1070407@linux.vnet.ibm.com> Subject: Re: [Qemu-devel] [PATCH 4/4] target-ppc: Handle NMI guest exit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aravinda Prasad Cc: Thomas Huth , benh@au1.ibm.com, aik@ozlabs.ru, agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, paulus@samba.org, sam.bobroff@au1.ibm.com --fLj60tP2PZ34xyqD Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Nov 12, 2015 at 11:53:45PM +0530, Aravinda Prasad wrote: >=20 >=20 > On Thursday 12 November 2015 01:39 PM, Thomas Huth wrote: > > On 11/11/15 18:16, Aravinda Prasad wrote: > >> Memory error such as bit flips that cannot be corrected > >> by hardware are passed on to the kernel for handling. > >> If the memory address in error belongs to guest then > >> guest kernel is responsible for taking suitable action. > >> Patch [1] enhances KVM to exit guest with exit reason > >> set to KVM_EXIT_NMI in such cases. > >> > >> This patch handles KVM_EXIT_NMI exit. If the guest OS > >> has registered the machine check handling routine by > >> calling "ibm,nmi-register", then the handler builds > >> the error log and invokes the registered handler else > >> invokes the handler at 0x200. > >> > >> [1] http://marc.info/?l=3Dkvm-ppc&m=3D144726114408289 > >> > >> Signed-off-by: Aravinda Prasad > >> --- > >> target-ppc/kvm.c | 69 +++++++++++++++++++++++++++++++++++++++++= ++ > >> target-ppc/kvm_ppc.h | 81 +++++++++++++++++++++++++++++++++++++++++= +++++++++ > >> 2 files changed, 150 insertions(+) > >> > >> diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c > >> index 110436d..e2e5170 100644 > >> --- a/target-ppc/kvm.c > >> +++ b/target-ppc/kvm.c > >> @@ -1665,6 +1665,11 @@ int kvm_arch_handle_exit(CPUState *cs, struct k= vm_run *run) > >> ret =3D 0; > >> break; > >> =20 > >> + case KVM_EXIT_NMI: > >> + DPRINTF("handle NMI exception\n"); > >> + ret =3D kvm_handle_nmi(cpu); > >> + break; > >> + > >> default: > >> fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_re= ason); > >> ret =3D -1; > >> @@ -2484,3 +2489,67 @@ int kvm_arch_msi_data_to_gsi(uint32_t data) > >> { > >> return data & 0xffff; > >> } > >> + > >> +int kvm_handle_nmi(PowerPCCPU *cpu) > >> +{ > >> + struct rtas_mc_log mc_log; > >> + CPUPPCState *env =3D &cpu->env; > >> + sPAPRMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); > >> + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); > >> + > >> + cpu_synchronize_state(CPU(ppc_env_get_cpu(env))); > >> + > >> + /* Properly set bits in MSR before we invoke the handler */ > >> + env->msr =3D 0; > >> + > >> + if (!(*pcc->interrupts_big_endian)(cpu)) { > >> + env->msr |=3D (1ULL << MSR_LE); > >> + } > >> + > >> +#ifdef TARGET_PPC64 > >> + env->msr |=3D (1ULL << MSR_SF); > >> +#endif > >> + > >> + if (!spapr->guest_machine_check_addr) { > >> + /* > >> + * If OS has not registered with "ibm,nmi-register" > >> + * jump to 0x200 > >> + */ > >=20 > > Shouldn't you also check MSR_ME here first and enter checkstop when > > machine checks are disabled? >=20 > Yes, MSR_ME should be checked first. >=20 > > Also I think you have to set up some more registers for machine check > > interrupts, like SRR0 and SRR1? >=20 > SRRO and SRR1 of vcpu are properly set in KVM in kvmppc_interrupt_hv. I > am not sure if any other registers need to be set. DAR and DSISR are the obvious ones you need to consider, although I suspect they're already set up correctly by the kernel, too. --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --fLj60tP2PZ34xyqD Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWRUO4AAoJEGw4ysog2bOShOAP/AimaZw2ZRxgjkV7ydxT/lrS inXvqSLlvvEOk5r/SzbvQnw+Nbxy3+tymvw2ZaQfC0OFR6KppYR+nonzWLqNOCgW iqOuU/NrfgGNJ+NfEcj2ZBfEq4f9IBUal90ckoAiUroqKudywSRc5Y6lA7IJyDiO rdSHXQMRy674KxE2ru5aLLcrkq3w63tz473VE1Qrk9aYQ6XMDlCUhLU3LL+FvWkR ICCf68UaPL2wD7+joNhY5LHd78bEnxZNLWLpsaXE80asF4Sp1B4RjJoFbKdoxa+R fVOsUyXTS91XvWBPdjARXrERy9wUh2mWo2PqNGmMUcBTkknOQlX7U2odrW/tKI7b Iscb+JIFiJF7hLDAihG+TW32WMMgEerLoWSUabT0t6PYOo/87N20O/1oBoMshyZB icm5QYgpfseLRBGkyi7WPxOXW8nEt1DzmJsd8TsgoAatmf/nGOMd84R1du9KAaEP bPe+hDY6gvFrrmHbG4l3+Sg0Z/dPRjczLj8jt1MzKrayD4rGGdrmA4AnQ4HmXKvp UUFn4cQHj07DU+k4+MjosMCH8FQrGkxeTpeh7ZZxokJctN5eHXXhZCTcNk8PHDyx t8Vd0yWedd9X8P7sCMKV+yQ9WNq6bRiuyR3SwccEZCP/mCEGomnF2LwzssIzsJtB hMfTDwRY1KBKS8O7fYab =53AJ -----END PGP SIGNATURE----- --fLj60tP2PZ34xyqD--