From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58843) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZyCYg-0007ii-Nz for qemu-devel@nongnu.org; Mon, 16 Nov 2015 00:42:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZyCYf-0007rg-B6 for qemu-devel@nongnu.org; Mon, 16 Nov 2015 00:42:30 -0500 Date: Mon, 16 Nov 2015 16:06:24 +1100 From: David Gibson Message-ID: <20151116050624.GD2747@voom.fritz.box> References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> <1447201710-10229-6-git-send-email-benh@kernel.crashing.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="IMjqdzrDRly81ofr" Content-Disposition: inline In-Reply-To: <1447201710-10229-6-git-send-email-benh@kernel.crashing.org> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 05/77] ppc: Update SPR definitions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org --IMjqdzrDRly81ofr Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Nov 11, 2015 at 11:27:18AM +1100, Benjamin Herrenschmidt wrote: > Add definitions for additional SPR numbers and SPR bit definitions > that will be relevant for subsequent improvements to POWER8 emulation >=20 > Also fix the definition of LPIDR which was incorrect (and is different > for server and embedded). >=20 > Signed-off-by: Benjamin Herrenschmidt > --- > target-ppc/cpu.h | 54 +++++++++++++++++++++++++++++++++++++++++++++++---= ---- > 1 file changed, 47 insertions(+), 7 deletions(-) >=20 > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index e6c43f9..611367f 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -470,9 +470,17 @@ struct ppc_slb_t { > #define MSR_RI 1 /* Recoverable interrupt 1 = */ > #define MSR_LE 0 /* Little-endian mode 1 hf= lags */ > =20 > -#define LPCR_ILE (1 << (63-38)) > -#define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */ > -#define LPCR_AIL (3 << LPCR_AIL_SHIFT) > +/* LPCR bits */ > +#define LPCR_VPM0 (1ull << (63-0)) > +#define LPCR_VPM1 (1ull << (63-1)) > +#define LPCR_ISL (1ull << (63-2)) > +#define LPCR_KBV (1ull << (63-3)) > +#define LPCR_ILE (1ull << (63-38)) > +#define LPCR_MER (1ull << (63-52)) > +#define LPCR_LPES0 (1ull << (63-60)) > +#define LPCR_LPES1 (1ull << (63-61)) > +#define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */ > +#define LPCR_AIL (3ull << LPCR_AIL_SHIFT) > =20 > #define msr_sf ((env->msr >> MSR_SF) & 1) > #define msr_isf ((env->msr >> MSR_ISF) & 1) > @@ -1338,6 +1346,10 @@ static inline int cpu_mmu_index (CPUPPCState *env,= bool ifetch) > #define SPR_UAMOR (0x09D) > #define SPR_MPC_ICTRL (0x09E) > #define SPR_MPC_BAR (0x09F) > +#define SPR_DAWR (0x0B4) > +#define SPR_RPR (0x0BA) > +#define SPR_DAWRX (0x0BC) > +#define SPR_HFSCR (0x0BE) > #define SPR_VRSAVE (0x100) > #define SPR_USPRG0 (0x100) > #define SPR_USPRG1 (0x101) > @@ -1392,19 +1404,25 @@ static inline int cpu_mmu_index (CPUPPCState *env= , bool ifetch) > #define SPR_HSRR1 (0x13B) > #define SPR_BOOKE_IAC4 (0x13B) > #define SPR_BOOKE_DAC1 (0x13C) > -#define SPR_LPIDR (0x13D) > +#define SPR_MMCRH (0x13C) > #define SPR_DABR2 (0x13D) > #define SPR_BOOKE_DAC2 (0x13D) > +#define SPR_TFMR (0x13D) > #define SPR_BOOKE_DVC1 (0x13E) > #define SPR_LPCR (0x13E) > #define SPR_BOOKE_DVC2 (0x13F) > +#define SPR_LPIDR (0x13F) > #define SPR_BOOKE_TSR (0x150) > +#define SPR_HMER (0x150) > +#define SPR_HMEER (0x151) > #define SPR_PCR (0x152) > +#define SPR_BOOKE_LPIDR (0x152) > #define SPR_BOOKE_TCR (0x154) > #define SPR_BOOKE_TLB0PS (0x158) > #define SPR_BOOKE_TLB1PS (0x159) > #define SPR_BOOKE_TLB2PS (0x15A) > #define SPR_BOOKE_TLB3PS (0x15B) > +#define SPR_AMOR (0x15D) > #define SPR_BOOKE_MAS7_MAS3 (0x174) > #define SPR_BOOKE_IVOR0 (0x190) > #define SPR_BOOKE_IVOR1 (0x191) > @@ -1622,6 +1640,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, = bool ifetch) > #define SPR_RCPU_L2U_RA3 (0x32B) > #define SPR_TAR (0x32F) > #define SPR_VTB (0x351) > +#define SPR_MMCRC (0x353) > #define SPR_440_INV0 (0x370) > #define SPR_440_INV1 (0x371) > #define SPR_440_INV2 (0x372) > @@ -1655,6 +1674,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, = bool ifetch) > #define SPR_440_DVLIM (0x398) > #define SPR_750_WPAR (0x399) > #define SPR_440_IVLIM (0x399) > +#define SPR_TSCR (0x399) > #define SPR_750_DMAU (0x39A) > #define SPR_750_DMAL (0x39B) > #define SPR_440_RSTCFG (0x39B) > @@ -1829,9 +1849,10 @@ static inline int cpu_mmu_index (CPUPPCState *env,= bool ifetch) > #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ > =20 > /* HID0 bits */ > -#define HID0_DEEPNAP (1 << 24) > -#define HID0_DOZE (1 << 23) > -#define HID0_NAP (1 << 22) > +#define HID0_DEEPNAP (1 << 24) /* pre-2.06 */ > +#define HID0_DOZE (1 << 23) /* pre-2.06 */ > +#define HID0_NAP (1 << 22) /* pre-2.06 */ > +#define HID0_HILE (1ull << (63-19)) /* POWER8 */ > =20 > /***********************************************************************= ******/ > /* PowerPC Instructions types definitions = */ > @@ -2180,6 +2201,25 @@ enum { > PCR_TM_DIS =3D 1ull << (63-2), /* Trans. memory disable (PO= WER8) */ > }; > =20 > +/* HMER/HMEER */ > +enum { Any particular reason for using an enum rather than defines like the rest? > + HMER_MALFUNCTION_ALERT =3D 1ull << (63-0), > + HMER_PROC_RECV_DONE =3D 1ull << (63-2), > + HMER_PROC_RECV_ERROR_MASKED =3D 1ull << (63-3), > + HMER_TFAC_ERROR =3D 1ull << (63-4), > + HMER_TFMR_PARITY_ERROR =3D 1ull << (63-5), > + HMER_XSCOM_FAIL =3D 1ull << (63-8), > + HMER_XSCOM_DONE =3D 1ull << (63-9), > + HMER_PROC_RECV_AGAIN =3D 1ull << (63-11), > + HMER_WARN_RISE =3D 1ull << (63-14), > + HMER_WARN_FALL =3D 1ull << (63-15), > + HMER_SCOM_FIR_HMI =3D 1ull << (63-16), > + HMER_TRIG_FIR_HMI =3D 1ull << (63-17), > + HMER_HYP_RESOURCE_ERR =3D 1ull << (63-20), > + HMER_XSCOM_STATUS_MASK =3D 7ull << (63-23), > + HMER_XSCOM_STATUS_LSH =3D (63-23), Is that last one correct? > +}; > + > /***********************************************************************= ******/ > =20 > static inline target_ulong cpu_read_xer(CPUPPCState *env) --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --IMjqdzrDRly81ofr Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWSWRPAAoJEGw4ysog2bOSCC8QAIAIPhwtqLkXs8fPhIOVjvlT qgXZBeqF4CdDRyG4ZR+bfcIx0LpLJCVffYGzPW0pezuUHsNvQEPRJvagqGj9Qy3H sjHrUHgGUcQXIkBKDkyiCR7U+aR97RKSE704SlRtNezT0eip7obAyMfm8+dENKpJ D/VevroGRHYvlLF51cTUkCb3bczHX7CN9WqAKasick61Vfg0z3KaBJHkBRUnceI2 2CbriWrQjlWWHBM9V5289pKtOqvJQ2faoHo+NWyObkEIE9GGvuyNV1M2JpRJ8geD e2hqI8P0OjqZz1DVKVXP7+daa1EBV9nsym9BnJwTMVmMyHELTieYFlo6jndTPkrw ZOXk0zbhvJmxGAcqkCj0FZu9SssS3y5K3gEyH+/f9zyWPus9SXxzE6QA5/5fbpUW IuTt3TvMO4S6bu9s8jSWbDomX18twYoAAx1QXNXGCaVG5+e8W1eNGAjpritAztGx sygJxtQOdHjC/wSTiKBTsFVPQXdZvFlGqXFOOL/zHW6ScKtDPsvah+b1bfGpRmU9 Nv5A9C4ZsV2V92EVO3k1ecCdu797QgpUl4908EW3hLGH91YU0u00/+CQ0YsufEpK qsR7occbN7GjXZSn4ZCesGx/W/nH+CNbrd9HKg2tIJ7zehVTSmILoii3P0YuD1wI puAOupRTRAGw/b2x1L1S =tYeQ -----END PGP SIGNATURE----- --IMjqdzrDRly81ofr--