From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZyCYi-0007me-DB for qemu-devel@nongnu.org; Mon, 16 Nov 2015 00:42:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZyCYg-0007s6-Ht for qemu-devel@nongnu.org; Mon, 16 Nov 2015 00:42:32 -0500 Date: Mon, 16 Nov 2015 16:30:13 +1100 From: David Gibson Message-ID: <20151116053013.GG2747@voom.fritz.box> References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> <1447201710-10229-12-git-send-email-benh@kernel.crashing.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="64j1qyTOoGvYcHb1" Content-Disposition: inline In-Reply-To: <1447201710-10229-12-git-send-email-benh@kernel.crashing.org> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 11/77] ppc: Create cpu_ppc_set_papr() helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org --64j1qyTOoGvYcHb1 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Nov 11, 2015 at 11:27:24AM +1100, Benjamin Herrenschmidt wrote: > And move the code adjusting the MSR mask and calling kvmppc_set_papr() > to it. This allows us to add a few more things such as disabling setting > of MSR:HV and appropriate LPCR bits which will be used when fixing > the exception model. >=20 > Signed-off-by: Benjamin Herrenschmidt Reviewed-by: David Gibson > --- > hw/ppc/spapr.c | 12 +++--------- > target-ppc/cpu.h | 1 + > target-ppc/translate_init.c | 37 ++++++++++++++++++++++++++++++++++++- > 3 files changed, 40 insertions(+), 10 deletions(-) >=20 > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index 37d071e..610629e 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -1606,15 +1606,8 @@ static void spapr_cpu_init(sPAPRMachineState *spap= r, PowerPCCPU *cpu) > /* Set time-base frequency to 512 MHz */ > cpu_ppc_tb_init(env, TIMEBASE_FREQ); > =20 > - /* PAPR always has exception vectors in RAM not ROM. To ensure this, > - * MSR[IP] should never be set. > - */ > - env->msr_mask &=3D ~(1 << 6); > - > - /* Tell KVM that we're in PAPR mode */ > - if (kvm_enabled()) { > - kvmppc_set_papr(cpu); > - } > + /* Enable PAPR mode in TCG or KVM */ > + cpu_ppc_set_papr(cpu); > =20 > if (cpu->max_compat) { > if (ppc_set_compat(cpu, cpu->max_compat) < 0) { > @@ -1791,6 +1784,7 @@ static void ppc_spapr_init(MachineState *machine) > fprintf(stderr, "Unable to find PowerPC CPU definition\n"); > exit(1); > } > + > spapr_cpu_init(spapr, cpu); > } > =20 > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 611367f..357b6e7 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1229,6 +1229,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulon= g val); > void store_booke_tsr (CPUPPCState *env, target_ulong val); > void ppc_tlb_invalidate_all (CPUPPCState *env); > void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); > +void cpu_ppc_set_papr(PowerPCCPU *cpu); > #endif > #endif > =20 > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 1d402e1..7bcfbc0 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -8423,8 +8423,43 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; > pcc->threads_per_core =3D 8; > } > -#endif /* defined (TARGET_PPC64) */ > =20 > +#if !defined(CONFIG_USER_ONLY) > + > +void cpu_ppc_set_papr(PowerPCCPU *cpu) > +{ > + CPUPPCState *env =3D &cpu->env; > + ppc_spr_t *lpcr =3D &env->spr_cb[SPR_LPCR]; > + > + /* PAPR always has exception vectors in RAM not ROM. To ensure this, > + * MSR[IP] should never be set. > + * > + * We also disallow setting of MSR_HV > + */ > + env->msr_mask &=3D ~((1ull << MSR_EP) | MSR_HVB); > + > + /* Set emulated LPCR to not send interrupts to hypervisor. Note that > + * under KVM, the actual HW LPCR will be set differently by KVM itse= lf, > + * the settings below ensure proper operations with TCG in absence of > + * a real hypervisor > + */ > + lpcr->default_value &=3D ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_K= BV); > + lpcr->default_value |=3D LPCR_LPES0 | LPCR_LPES1; > + > + /* We should be followed by a CPU reset but update the active value > + * just in case... > + */ > + env->spr[SPR_LPCR] =3D lpcr->default_value; > + > + /* Tell KVM that we're in PAPR mode */ > + if (kvm_enabled()) { > + kvmppc_set_papr(cpu); > + } > +} > + > +#endif /* !defined(CONFIG_USER_ONLY) */ > + > +#endif /* defined (TARGET_PPC64) */ > =20 > /***********************************************************************= ******/ > /* Generic CPU instantiation routine = */ --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --64j1qyTOoGvYcHb1 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWSWnlAAoJEGw4ysog2bOSUhQQANf/+v0LyGFmj/O2JSA1hrQj h95/k+b8KKK95arAWfAX99F2zxp5L+bVIoHvz0YVR4ays3URyxBurQBRj2/3pgwv Z1HJITsHXEBPkfG0yZdQETGNmzXQzjMgmykXF7n8TRKyv2O3qyKcG78XhqF2gFSJ rsfcpYx19nvO2Dn0x0408+wOJ4RH15seUCnn7CbRIk9TjrHWKKbSWVhPj5NfefKf ntMRqj4ukajNOd/yJjY4q5lRyxzkALM/81Ffw+BRaRQ/nAovPPVJMDClVvsxtrR0 D3Sxjn94QNVogkTaLOAoNv741SdbIA2c3NN12ZYhrceyBHWRSrhclW4iQK92kep3 SROQ+zNfrCs4f7H65WhuU+KivwAvDQVR+obj6Od2t5Fw56ShFUe5cV5/EGfQtv/Y UEBme+kAk5tSlzzGsYeQ3hVcBfeD5SwjJpVnTefELLDxlxt7wVtTBne8s4rHVs3W HaDXABctJMfZgdHB8Iq6n+wsKi4GjOaeoXkwGl3LTa/JwhWDK36QAohmrTlwVJa2 E8OhoWOHdAQudY687f/0ryTcGaIloH8jKmMdv+g/jIJJP6Xgs4bkMb+yuGenBFyB xOVrtKchiVz33vmJmcuGGqM1W/m6FqBP4yTWw21RhXDXo4G4mbSXdbIr7qSjKw5X Fg0blZux8no1Yi+J0Zsx =gLVI -----END PGP SIGNATURE----- --64j1qyTOoGvYcHb1--