From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46618) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZzLzX-0002n3-G6 for qemu-devel@nongnu.org; Thu, 19 Nov 2015 04:59:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZzLzF-0006pB-2J for qemu-devel@nongnu.org; Thu, 19 Nov 2015 04:58:59 -0500 Date: Thu, 19 Nov 2015 17:22:27 +1100 From: David Gibson Message-ID: <20151119062227.GE10667@voom.redhat.com> References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> <1447201710-10229-13-git-send-email-benh@kernel.crashing.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="ffoCPvUAPMgSXi6H" Content-Disposition: inline In-Reply-To: <1447201710-10229-13-git-send-email-benh@kernel.crashing.org> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 12/77] ppc: Better figure out if processor has HV mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org --ffoCPvUAPMgSXi6H Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Nov 11, 2015 at 11:27:25AM +1100, Benjamin Herrenschmidt wrote: > We use an env. flag which is set to the initial value of MSR_HVB in > the msr_mask. We also adjust the POWER8 mask to set SHV. >=20 > Also use this to adjust ctx.hv so that it is *set* when the processor > doesn't have an HV mode (970 with Apple mode for example), thus enabling > hypervisor instructions/SPRs. >=20 > Signed-off-by: Benjamin Herrenschmidt Reviewed-by: David Gibson > --- > target-ppc/cpu.h | 4 ++++ > target-ppc/translate.c | 4 +++- > target-ppc/translate_init.c | 21 ++++++++++++++++----- > 3 files changed, 23 insertions(+), 6 deletions(-) >=20 > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 357b6e7..062644e 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1113,6 +1113,10 @@ struct CPUPPCState { > hwaddr mpic_iack; > /* true when the external proxy facility mode is enabled */ > bool mpic_proxy; > + /* set when the processor has an HV mode, thus HV priv > + * instructions and SPRs are diallowed if MSR:HV is 0 > + */ > + bool has_hv_mode; > #endif > =20 > /* Those resources are used only during code translation */ > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index a2fe1b5..10eb9e3 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -11465,8 +11465,10 @@ void gen_intermediate_code(CPUPPCState *env, str= uct TranslationBlock *tb) > ctx.exception =3D POWERPC_EXCP_NONE; > ctx.spr_cb =3D env->spr_cb; > ctx.pr =3D msr_pr; > - ctx.hv =3D !msr_pr && msr_hv; > ctx.mem_idx =3D env->dmmu_idx; > +#if !defined(CONFIG_USER_ONLY) > + ctx.hv =3D !msr_pr && (msr_hv || !env->has_hv_mode); > +#endif > ctx.insns_flags =3D env->insns_flags; > ctx.insns_flags2 =3D env->insns_flags2; > ctx.access_type =3D -1; > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 7bcfbc0..76f20ea 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -8391,7 +8391,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | > PPC2_TM; > pcc->msr_mask =3D (1ull << MSR_SF) | > - (1ull << MSR_TM) | > + (1ull << MSR_SHV) | > + (1ull << MSR_TM) | > (1ull << MSR_VR) | > (1ull << MSR_VSX) | > (1ull << MSR_EE) | > @@ -9748,10 +9749,7 @@ static void ppc_cpu_reset(CPUState *s) > pcc->parent_reset(s); > =20 > msr =3D (target_ulong)0; > - if (0) { > - /* XXX: find a suitable condition to enable the hypervisor mode = */ > - msr |=3D (target_ulong)MSR_HVB; > - } > + msr |=3D (target_ulong)MSR_HVB; > msr |=3D (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ > msr |=3D (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ > msr |=3D (target_ulong)1 << MSR_EP; > @@ -9852,6 +9850,19 @@ static void ppc_cpu_initfn(Object *obj) > env->bfd_mach =3D pcc->bfd_mach; > env->check_pow =3D pcc->check_pow; > =20 > + /* Mark HV mode as supported if the CPU has an MSR_HV bit > + * in the msr_mask. The mask can later be cleared by PAPR > + * mode but the hv mode support will remain, thus enforcing > + * that we cannot use priv. instructions in guest in PAPR > + * mode. For 970 we currently simply don't set HV in msr_mask > + * thus simulating an "Apple mode" 970. If we ever want to > + * support 970 HV mode, we'll have to add a processor attribute > + * of some sort. > + */ > +#if !defined(CONFIG_USER_ONLY) > + env->has_hv_mode =3D !!(env->msr_mask & MSR_HVB); > +#endif > + > #if defined(TARGET_PPC64) > if (pcc->sps) { > env->sps =3D *pcc->sps; --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --ffoCPvUAPMgSXi6H Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWTWqjAAoJEGw4ysog2bOSa4QP/jfXSGDcQD+jUko3lLS5kCwY 1AZnN1n5WMIjS7jiw6qA23+NpmSvfa4+STrBR55H6dJzoc4YWr/SezlrkrsBUvgz /9qCNJXjaUGbz1djriiZl3EWzlTXoLmm3OA8sA2mzZRXZW+EAs3EV7KEy7o3gjWA J9UjpPLKsx894Jpgqje4QLQHwakVrQCLfhwt+i9iv7RT5+cZGYQhL7g2Y7JvXfh9 zREpFAeY8JzYkSpJeklebhmj5y+x+U6Pb6Yap8KtS/nLleG9llJm5Aesdy1risx8 C7Ps7XDt1sgLc4LGAeFlmlao7j8k5o6cDGkl3HXK0dNkQfusP23iqYiDel1DJTRU CLMTq/eeshpCvcE+gXypDOg4KCGL8Q0UL0022O14RaCysWXJAzytK5km8Xvvy0Yy VVaFoOIS/AihKgQA583wRmwAFYjPW0UES2uJPlTWty+IdOG6PVrUx2HOHmH1vl8P Za71Y780SxnCh+BP6ZpDJM/mUzIyPEpwHZoJoxNkvBYkA4Ikr5hVjOG9iCCgsX5/ 1G9Qy1Z6jx1aof6GHqSN6fVomF/5wF6BjFR8BnVATSgVuPWZSgVi/fvqHcZxgbch KV5VEO4PCO8Jc56ON5R4NQ8fTzQKSGcMXZlTcXtSfSPfAPmH20OdCL6JpfFUoKeJ uM5nhCkLTrP2p6fiA0Bs =Uu7c -----END PGP SIGNATURE----- --ffoCPvUAPMgSXi6H--