From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47486) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZzLzt-0002zx-1s for qemu-devel@nongnu.org; Thu, 19 Nov 2015 04:59:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZzLzF-0006qA-Tg for qemu-devel@nongnu.org; Thu, 19 Nov 2015 04:59:20 -0500 Date: Thu, 19 Nov 2015 17:50:57 +1100 From: David Gibson Message-ID: <20151119065057.GI10667@voom.redhat.com> References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> <1447201710-10229-21-git-send-email-benh@kernel.crashing.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="PWfwoUCx3AFJRUBq" Content-Disposition: inline In-Reply-To: <1447201710-10229-21-git-send-email-benh@kernel.crashing.org> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 20/77] ppc: Fix generation if ISI/DSI vs. HV mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org --PWfwoUCx3AFJRUBq Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Nov 11, 2015 at 11:27:33AM +1100, Benjamin Herrenschmidt wrote: > Under some circumstances, we need to direct ISI and DSI interrupts > at the hypervisor, turning them into HISI/HDSI, and using different > SPRs (HDSISR and HDAR) depending on the combination of MSR_DR and > the corresponding VPM bits in LPCR. >=20 > This moves part of the code into helpers that are fixed to select > the right exception type and registers. On pre-P7 processors, LPCR > is 0 which provides the old behaviour of directing the interrupts > at the supervisor. >=20 > Thanks to Andrei Warkentin for finding a bug when HV=3D1 >=20 > Signed-off-by: Benjamin Herrenschmidt Reviewed-by: David Gibson > --- > target-ppc/mmu-hash64.c | 66 +++++++++++++++++++++++++++++++++++--------= ------ > 1 file changed, 47 insertions(+), 19 deletions(-) >=20 > diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c > index 71e1d14..e489fa4 100644 > --- a/target-ppc/mmu-hash64.c > +++ b/target-ppc/mmu-hash64.c > @@ -466,6 +466,44 @@ static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, p= pc_hash_pte64_t pte, > return (rpn & ~mask) | (eaddr & mask); > } > =20 > +static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env, uint64_t = error_code) > +{ > + bool vpm; > + > + if (msr_ir) { > + vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); > + } else { > + vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); > + } > + if (vpm && !msr_hv) { > + cs->exception_index =3D POWERPC_EXCP_HISI; > + } else { > + cs->exception_index =3D POWERPC_EXCP_ISI; > + } > + env->error_code =3D error_code; > +} > + > +static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t = dar, uint64_t dsisr) > +{ > + bool vpm; > + > + if (msr_dr) { > + vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); > + } else { > + vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); > + } > + if (vpm && msr_hv) { > + cs->exception_index =3D POWERPC_EXCP_HDSI; > + env->spr[SPR_HDAR] =3D dar; > + env->spr[SPR_HDSISR] =3D dsisr; > + } else { > + cs->exception_index =3D POWERPC_EXCP_DSI; > + env->spr[SPR_DAR] =3D dar; > + env->spr[SPR_DSISR] =3D dsisr; > + } > + env->error_code =3D 0; > +} > + > int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, > int rwx, int mmu_idx) > { > @@ -475,7 +513,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, targ= et_ulong eaddr, > hwaddr pte_offset; > ppc_hash_pte64_t pte; > int pp_prot, amr_prot, prot; > - uint64_t new_pte1; > + uint64_t new_pte1, dsisr; > const int need_prot[] =3D {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; > hwaddr raddr; > =20 > @@ -509,26 +547,21 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, ta= rget_ulong eaddr, > =20 > /* 3. Check for segment level no-execute violation */ > if ((rwx =3D=3D 2) && (slb->vsid & SLB_VSID_N)) { > - cs->exception_index =3D POWERPC_EXCP_ISI; > - env->error_code =3D 0x10000000; > + ppc_hash64_set_isi(cs, env, 0x10000000); > return 1; > } > =20 > /* 4. Locate the PTE in the hash table */ > pte_offset =3D ppc_hash64_htab_lookup(env, slb, eaddr, &pte); > if (pte_offset =3D=3D -1) { > + dsisr =3D 0x40000000; > if (rwx =3D=3D 2) { > - cs->exception_index =3D POWERPC_EXCP_ISI; > - env->error_code =3D 0x40000000; > + ppc_hash64_set_isi(cs, env, dsisr); > } else { > - cs->exception_index =3D POWERPC_EXCP_DSI; > - env->error_code =3D 0; > - env->spr[SPR_DAR] =3D eaddr; > if (rwx =3D=3D 1) { > - env->spr[SPR_DSISR] =3D 0x42000000; > - } else { > - env->spr[SPR_DSISR] =3D 0x40000000; > + dsisr |=3D 0x02000000; > } > + ppc_hash64_set_dsi(cs, env, eaddr, dsisr); > } > return 1; > } > @@ -545,14 +578,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, tar= get_ulong eaddr, > /* Access right violation */ > qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); > if (rwx =3D=3D 2) { > - cs->exception_index =3D POWERPC_EXCP_ISI; > - env->error_code =3D 0x08000000; > + ppc_hash64_set_isi(cs, env, 0x08000000); > } else { > - target_ulong dsisr =3D 0; > - > - cs->exception_index =3D POWERPC_EXCP_DSI; > - env->error_code =3D 0; > - env->spr[SPR_DAR] =3D eaddr; > + dsisr =3D 0; > if (need_prot[rwx] & ~pp_prot) { > dsisr |=3D 0x08000000; > } > @@ -562,7 +590,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, targ= et_ulong eaddr, > if (need_prot[rwx] & ~amr_prot) { > dsisr |=3D 0x00200000; > } > - env->spr[SPR_DSISR] =3D dsisr; > + ppc_hash64_set_dsi(cs, env, eaddr, dsisr); > } > return 1; > } --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --PWfwoUCx3AFJRUBq Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWTXFRAAoJEGw4ysog2bOSNEAP/1s3ZzxertaMWxFRHJhxO4tw XU1O8g5HjmdyT+MrBNHxeAPuWfTh0u4qqaQ3dgwXhYJcoo7/rUVOXd/Dn/AN+xkl //mGJexGBSDq+nBx274xYdGzXsg/wA0Zdozcc8gFuKKChKiKThXYqJpcVIk5D1LX fTKOhrztBC7eoPfl8H5jucIO1TECLnt968HoRO1t1tF38QLx1DjPmwV/CBqPM4hC glihNMGJwGrc9sDO/0gBUkPrGxNhVh3wUYRyzQFDqm53mTQqk8xGF3twyxPH8XE+ FT/SRNkDeibQohUWYBysbA0Hrhz/AL/dIQvj3Pq8ikIrMfyN3hA62NT4r8hYHrio m/n2WnaNmfm6eydl/RBzwqSgPYv8WhNtAy9DvdQoQvqLdpmz3+T7CSGxAvap39Bu XXxDnkCq1sqbujiZTES+55cViQTVrP+dtcmoHpRGIQucfJZpwpyjTUYIhM1/Y0Jj rDXL/0a6vrQUOULzmhvafCE00mBPfPFxGDyGSMs22RH+ZuoejcU0KYZTuvgLSzgo 6anUnGDO5sLoYGRtfz29e8wIMPuwmPJy092trOCvKjyppSvlTc6GtkoQqOf3WVWt 3ebP4ckwhxLmlLeG6BOKpy/t7U1o2f0QrAaiNjMhduJZJSPNwi1v99FGR1F6Cxoa rjtU+O6tEd4O9oJ01caa =gSJE -----END PGP SIGNATURE----- --PWfwoUCx3AFJRUBq--