From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33565) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a0sf3-0002Ei-BX for qemu-devel@nongnu.org; Mon, 23 Nov 2015 10:04:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a0sez-00078k-8O for qemu-devel@nongnu.org; Mon, 23 Nov 2015 10:04:09 -0500 Received: from mail.skyhub.de ([2a01:4f8:120:8448::d00d]:44351) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a0sez-00077x-2V for qemu-devel@nongnu.org; Mon, 23 Nov 2015 10:04:05 -0500 Date: Mon, 23 Nov 2015 16:03:55 +0100 From: Borislav Petkov Message-ID: <20151123150355.GE5134@pd.tnic> References: <1448060471-14128-1-git-send-email-bp@alien8.de> <564FA8A7.3000500@suse.de> <20151121010925.GB3994@pd.tnic> <20151123132237.GM23717@thinpad.lan.raisama.net> <56532710.8030607@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <56532710.8030607@redhat.com> Subject: Re: [Qemu-devel] [PATCH] target-i386: Do not set MCG_SER_P by default List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , Eduardo Habkost Cc: Tony Luck , KVM , Marcelo Tosatti , qemu-devel , Huang Ying , Andreas =?utf-8?Q?F=C3=A4rber?= , Richard Henderson + Tony. On Mon, Nov 23, 2015 at 03:47:44PM +0100, Paolo Bonzini wrote: > On 23/11/2015 14:22, Eduardo Habkost wrote: > > > Software Error Recovery, i.e. SER, is purely an Intel feature and it > > > shouldn't be set by default. Enable it only on Intel. > > > > What happens when SER is enabled on an AMD CPU? If it really > > should't be enabled, why is KVM returning it on > > KVM_X86_GET_MCE_CAP_SUPPORTED? > > Indeed... is it a problem if our frankenstein AMD CPU can recover from > memory errors? The problem stems from the fact that the guest kernel looks at SER and does different handling depending on that bit: machine_check_poll: ... if (!(flags & MCP_UC) && (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) continue; so when the guest kernel gets a correctable error (injected..., for example) it sees that bit set. Even though kvm/qemu emulates an AMD CPU. So on AMD with that bit set, it would puzzle the whole error handling/reporting in the guest kernel. Oh, btw, I'm using a kvm guest to inject MCEs. In case you were wondering why is he even doing that. :-) And I'm not sure it makes sense to set that bit for an Intel guest too. For the simple reason that I don't know how much of the Software Error Recovery stuff is actually implemented there. If stuff is missing, you probably don't want to advertize it there too. And by "stuff" I mean all that fun in section "15.6 RECOVERY OF UNCORRECTED RECOVERABLE (UCR) ERRORS" of the SDM. It's a whole another question how/whether to do UCR error handling in the guest or maybe leave it to the host... -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply.