From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38072) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a16fH-0004Cx-VJ for qemu-devel@nongnu.org; Tue, 24 Nov 2015 01:01:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a16fE-0001K9-Uq for qemu-devel@nongnu.org; Tue, 24 Nov 2015 01:01:19 -0500 Date: Tue, 24 Nov 2015 14:20:50 +1100 From: David Gibson Message-ID: <20151124032050.GG26118@voom.fritz.box> References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> <1447201710-10229-28-git-send-email-benh@kernel.crashing.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="doKZ0ri6bHmN2Q5y" Content-Disposition: inline In-Reply-To: <1447201710-10229-28-git-send-email-benh@kernel.crashing.org> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 27/77] ppc/pnv: Add XSCOM infrastructure List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org --doKZ0ri6bHmN2Q5y Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Nov 11, 2015 at 11:27:40AM +1100, Benjamin Herrenschmidt wrote: > XSCOM is an interface to a sideband bus provided by the POWER8 chip > pervasive unit, which gives access to a number of facilities in the > chip that are needed by the OPAL firmware and to a lesser extent, > Linux. This is among others how the PCI Host bridges get configured > at boot or how the LPC bus is accessed. >=20 > This provides a simple bus and device type for devices sitting on > XSCOM along with some facilities to optionally generate corresponding > device-tree nodes >=20 > Signed-off-by: Benjamin Herrenschmidt > --- > hw/ppc/Makefile.objs | 2 +- > hw/ppc/pnv.c | 11 ++ > hw/ppc/pnv_xscom.c | 415 +++++++++++++++++++++++++++++++++++++++= ++++++ > include/hw/ppc/pnv.h | 2 + > include/hw/ppc/pnv_xscom.h | 73 ++++++++ > 5 files changed, 502 insertions(+), 1 deletion(-) > create mode 100644 hw/ppc/pnv_xscom.c > create mode 100644 include/hw/ppc/pnv_xscom.h >=20 > diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs > index cd74c96..2a7dd42 100644 > --- a/hw/ppc/Makefile.objs > +++ b/hw/ppc/Makefile.objs > @@ -5,7 +5,7 @@ obj-$(CONFIG_PSERIES) +=3D spapr.o spapr_vio.o spapr_even= ts.o > obj-$(CONFIG_PSERIES) +=3D spapr_hcall.o spapr_iommu.o spapr_rtas.o > obj-$(CONFIG_PSERIES) +=3D spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng= =2Eo > # IBM PowerNV > -obj-$(CONFIG_POWERNV) +=3D pnv.o > +obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o > ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy) > obj-y +=3D spapr_pci_vfio.o > endif > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index e68c9b1..2eac877 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -41,6 +41,7 @@ > #include "hw/ppc/ppc.h" > #include "hw/ppc/pnv.h" > #include "hw/loader.h" > +#include "hw/ppc/pnv_xscom.h" > =20 > #include "exec/address-spaces.h" > #include "qemu/config-file.h" > @@ -310,6 +311,7 @@ static void *powernv_create_fdt(PnvSystem *sys, uint3= 2_t initrd_base, uint32_t i > uint32_t end_prop =3D cpu_to_be32(initrd_base + initrd_size); > char *buf; > const char plat_compat[] =3D "qemu,powernv\0ibm,powernv"; > + unsigned int i; > =20 > fdt =3D g_malloc0(FDT_MAX_SIZE); > _FDT((fdt_create(fdt, FDT_MAX_SIZE))); > @@ -367,6 +369,12 @@ static void *powernv_create_fdt(PnvSystem *sys, uint= 32_t initrd_base, uint32_t i > /* Memory */ > _FDT((powernv_populate_memory(fdt))); > =20 > + /* For each chip */ > + for (i =3D 0; i < sys->num_chips; i++) { > + /* Populate XSCOM */ > + _FDT((xscom_populate_fdt(sys->chips[i].xscom, fdt))); > + } > + > /* /hypervisor node */ > if (kvm_enabled()) { > uint8_t hypercall[16]; > @@ -424,6 +432,9 @@ static void pnv_create_chip(PnvSystem *sys, unsigned = int chip_no) > =20 > /* XXX Improve chip numbering to better match HW */ > chip->chip_id =3D chip_no; > + > + /* Set up XSCOM bus */ > + xscom_create(chip); Hmm.. I'm thinking it probably makes sense to unify the representation of "chip" and "xscom" since there's a 1:1 correspondance. To be QOMishly correct, I think the right way would be a SysBusDevice for each chip, implementing the xscom MMIOs, then an array of link properties under the Machine object to find the right scoms by chip id. > } > =20 > static void ppc_powernv_init(MachineState *machine) > diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c > new file mode 100644 > index 0000000..bb35422 > --- /dev/null > +++ b/hw/ppc/pnv_xscom.c > @@ -0,0 +1,415 @@ > + > +/* > + * QEMU PowerNV XSCOM bus definitions > + * > + * Copyright (c) 2010 David Gibson, IBM Corporation > + * Based on the s390 virtio bus code: > + * Copyright (c) 2009 Alexander Graf > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +/* TODO: Add some infrastructure for "random stuff" and FIRs that > + * various units might want to deal with without creating actual > + * XSCOM devices. > + * > + * For example, HB LPC XSCOM in the PIBAM > + */ > +#include "hw/hw.h" > +#include "sysemu/sysemu.h" > +#include "hw/boards.h" > +#include "monitor/monitor.h" > +#include "hw/loader.h" > +#include "elf.h" > +#include "hw/sysbus.h" > +#include "sysemu/kvm.h" > +#include "sysemu/device_tree.h" > +#include "kvm_ppc.h" > + > +#include "hw/ppc/pnv_xscom.h" > + > +#include > + > +#define TYPE_XSCOM "xscom" > +#define XSCOM(obj) OBJECT_CHECK(XScomState, (obj), TYPE_XSCOM) > + > +#define XSCOM_SIZE 0x800000000ull > +#define XSCOM_BASE(chip) (0x3fc0000000000ull + ((uint64_t)(chip)) * XSC= OM_SIZE) > + > +//#define TRACE_SCOMS > + > +typedef struct XScomState { > + /*< private >*/ > + SysBusDevice parent_obj; > + /*< public >*/ > + > + MemoryRegion mem; > + int32_t chip_id; > + XScomBus *bus; > +} XScomState; > + > +static uint32_t xscom_to_pcb_addr(uint64_t addr) > +{ > + addr &=3D (XSCOM_SIZE - 1); > + return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); Wow, that's a pretty weird address transform. > +} > + > +static void xscom_complete(uint64_t hmer_bits) > +{ > + CPUState *cs =3D current_cpu; > + PowerPCCPU *cpu =3D POWERPC_CPU(cs); > + CPUPPCState *env =3D &cpu->env; > + > + cpu_synchronize_state(cs); > + env->spr[SPR_HMER] |=3D hmer_bits; > + > + /* XXX Need a CPU helper to set HMER, also handle gneeration > + * of HMIs Not sure what you're referring to here. Nothing more should be needed to set the HMER - because you've called cpu_synchronize_state() it will be marked dirty and flushed back to KVM before re-entry. > + */ > +} > + > +static XScomDevice *xscom_find_target(XScomState *s, uint32_t pcb_addr, = uint32_t *range) > +{ > + BusChild *bc; > + > + QTAILQ_FOREACH(bc, &s->bus->bus.children, sibling) { > + DeviceState *qd =3D bc->child; > + XScomDevice *xd =3D XSCOM_DEVICE(qd); > + unsigned int i; > + > + for (i =3D 0; i < MAX_XSCOM_RANGES; i++) { > + if (xd->ranges[i].addr <=3D pcb_addr && > + (xd->ranges[i].addr + xd->ranges[i].size) > pcb_addr) { > + *range =3D i; > + return xd; > + } > + } > + } I'm wondering if it makes sense to construct a custom AddressSpace and use the existing address space lookup logic from exec.c and memory.c rather than implementing your own. > + return NULL; > +} > + > +static bool xscom_dispatch_read(XScomState *s, uint32_t pcb_addr, uint64= _t *out_val) > +{ > + uint32_t range, offset; > + struct XScomDevice *xd =3D xscom_find_target(s, pcb_addr, &range); > + XScomDeviceClass *xc; > + > + if (!xd) { > + return false; > + } > + xc =3D XSCOM_DEVICE_GET_CLASS(xd); > + if (!xc->read) { > + return false; > + } > + offset =3D pcb_addr - xd->ranges[range].addr; > + return xc->read(xd, range, offset, out_val); > +} > + > +static bool xscom_dispatch_write(XScomState *s, uint32_t pcb_addr, uint6= 4_t val) > +{ > + uint32_t range, offset; > + struct XScomDevice *xd =3D xscom_find_target(s, pcb_addr, &range); > + XScomDeviceClass *xc; > + > + if (!xd) { > + return false; > + } > + xc =3D XSCOM_DEVICE_GET_CLASS(xd); > + if (!xc->write) { > + return false; > + } > + offset =3D pcb_addr - xd->ranges[range].addr; > + return xc->write(xd, range, offset, val); > +} > + > +static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width) > +{ > + XScomState *s =3D opaque; > + uint32_t pcba =3D xscom_to_pcb_addr(addr); > + uint64_t val; > + > + assert(width =3D=3D 8); > + > +#ifdef TRACE_SCOMS > + printf("XSCOM_READ(0x%x:0x%x)\n", s->chip_id, pcba); > +#endif You should be using the built in trace infrastructure here - it's really not that much of a pain. Put trace_xscom_read(s->chip_id, pcba) here, put a suitable format in trace-events, and ./configure --enable-trace-backends=3Dstderr > + > + /* Handle some SCOMs here before dispatch */ > + switch(pcba) { > + case 0xf000f: > + val =3D 0x221EF04980000000; > + break; > + case 0x1010c00: /* PIBAM FIR */ > + case 0x1010c03: /* PIBAM FIR MASK */ > + case 0x2020007: /* ADU stuff */ > + case 0x2020009: /* ADU stuff */ > + case 0x202000f: /* ADU stuff */ > + val =3D 0; > + break; > + case 0x2013f00: /* PBA stuff */ > + case 0x2013f01: /* PBA stuff */ > + case 0x2013f02: /* PBA stuff */ > + case 0x2013f03: /* PBA stuff */ > + case 0x2013f04: /* PBA stuff */ > + case 0x2013f05: /* PBA stuff */ > + case 0x2013f06: /* PBA stuff */ > + case 0x2013f07: /* PBA stuff */ > + val =3D 0; > + break; > + default: > + if (!xscom_dispatch_read(s, pcba, &val)) { > + xscom_complete(HMER_XSCOM_FAIL | HMER_XSCOM_DONE); > + return 0; > + } > + } > + > + xscom_complete(HMER_XSCOM_DONE); > + return val; > +} > + > +static void xscom_write(void *opaque, hwaddr addr, uint64_t val, > + unsigned width) > +{ > + XScomState *s =3D opaque; > + uint32_t pcba =3D xscom_to_pcb_addr(addr); > + > + assert(width =3D=3D 8); > + > +#ifdef TRACE_SCOMS > + printf("XSCOM_WRITE(0x%x:0x%x, 0x%016llx)\n", > + s->chip_id, pcba, (unsigned long long)val); > +#endif > + /* Handle some SCOMs here before dispatch */ > + switch(pcba) { > + /* We ignore writes to these */ > + case 0xf000f: /* chip id is RO */ > + case 0x1010c00: /* PIBAM FIR */ > + case 0x1010c01: /* PIBAM FIR */ > + case 0x1010c02: /* PIBAM FIR */ > + case 0x1010c03: /* PIBAM FIR MASK */ > + case 0x1010c04: /* PIBAM FIR MASK */ > + case 0x1010c05: /* PIBAM FIR MASK */ > + case 0x2020007: /* ADU stuff */ > + case 0x2020009: /* ADU stuff */ > + case 0x202000f: /* ADU stuff */ > + break; > + default: > + if (!xscom_dispatch_write(s, pcba, val)) { > + xscom_complete(HMER_XSCOM_FAIL | HMER_XSCOM_DONE); > + return; > + } > + } > + > + xscom_complete(HMER_XSCOM_DONE); > +} > + > +static const MemoryRegionOps xscom_ops =3D { > + .read =3D xscom_read, > + .write =3D xscom_write, > + .valid.min_access_size =3D 8, > + .valid.max_access_size =3D 8, > + .impl.min_access_size =3D 8, > + .impl.max_access_size =3D 8, > + .endianness =3D DEVICE_BIG_ENDIAN, > +}; > + > +static int xscom_init(SysBusDevice *dev) > +{ > + XScomState *s =3D XSCOM(dev); > + > + s->chip_id =3D -1; > + return 0; > +} > + > +static void xscom_realize(DeviceState *dev, Error **errp) > +{ > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); > + XScomState *s =3D XSCOM(dev); > + char *name; > + > + assert(s->chip_id >=3D 0); So, this assert could be tripped if the user explicitly instantiated an xscom device which they probably shouldn't do, but could. So, it probably makes sense to use error_setg() here instead of assert(). > + name =3D g_strdup_printf("xscom-%x", s->chip_id); > + memory_region_init_io(&s->mem, OBJECT(s), &xscom_ops, s, name, XSCOM= _SIZE); > + sysbus_init_mmio(sbd, &s->mem); > + sysbus_mmio_map(sbd, 0, XSCOM_BASE(s->chip_id)); > +} > + > +static Property xscom_properties[] =3D { > + DEFINE_PROP_INT32("chip_id", XScomState, chip_id, 0), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void xscom_class_init(ObjectClass *klass, void *data) > +{ > + SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); > + DeviceClass *dc =3D DEVICE_CLASS(klass); > + > + dc->props =3D xscom_properties; > + dc->realize =3D xscom_realize; > + k->init =3D xscom_init; > +} > + > +static const TypeInfo xscom_info =3D { > + .name =3D TYPE_XSCOM, > + .parent =3D TYPE_SYS_BUS_DEVICE, > + .instance_size =3D sizeof(XScomState), > + .class_init =3D xscom_class_init, > +}; > + > +static void xscom_bus_class_init(ObjectClass *klass, void *data) > +{ > +} > + > +static const TypeInfo xscom_bus_info =3D { > + .name =3D TYPE_XSCOM_BUS, > + .parent =3D TYPE_BUS, > + .class_init =3D xscom_bus_class_init, > + .instance_size =3D sizeof(XScomBus), > +}; > + > +void xscom_create(PnvChip *chip) > +{ > + DeviceState *dev; > + XScomState *xdev; > + BusState *qbus; > + XScomBus *xb; > + > + dev =3D qdev_create(NULL, TYPE_XSCOM); > + qdev_prop_set_uint32(dev, "chip_id", chip->chip_id); > + qdev_init_nofail(dev); > + > + /* Create bus on bridge device */ > + qbus =3D qbus_create(TYPE_XSCOM_BUS, dev, "xscom"); > + xb =3D DO_UPCAST(XScomBus, bus, qbus); > + xb->chip_id =3D chip->chip_id; > + xdev =3D XSCOM(dev); > + xdev->bus =3D xb; > + chip->xscom =3D xb; I believe the qbus_create() is usually invoked by the bridge's init function, rather than externally. > +} > + > +#define _FDT(exp) \ > + do { \ > + int ret =3D (exp); \ > + if (ret < 0) { \ > + fprintf(stderr, "qemu: error creating device tree: %s: %s\n"= , \ > + #exp, fdt_strerror(ret)); \ > + exit(1); \ > + } \ > + } while (0) > + > + > +int xscom_populate_fdt(XScomBus *xb, void *fdt) > +{ > + BusChild *bc; > + char *name; > + const char compat[] =3D "ibm,power8-xscom\0ibm,xscom"; > + uint64_t reg[] =3D { cpu_to_be64(XSCOM_BASE(xb->chip_id)), > + cpu_to_be64(XSCOM_SIZE) }; > + > + name =3D g_strdup_printf("xscom@%llx", (unsigned long long)be64_to_c= pu(reg[0])); > + _FDT((fdt_begin_node(fdt, name))); > + g_free(name); > + _FDT((fdt_property_cell(fdt, "ibm,chip-id", xb->chip_id))); > + _FDT((fdt_property_cell(fdt, "#address-cells", 1))); > + _FDT((fdt_property_cell(fdt, "#size-cells", 1))); > + _FDT((fdt_property(fdt, "reg", reg, sizeof(reg)))); > + _FDT((fdt_property(fdt, "compatible", compat, sizeof(compat))));=20 > + _FDT((fdt_property(fdt, "scom-controller", NULL, 0)));=20 > + > + QTAILQ_FOREACH(bc, &xb->bus.children, sibling) { > + DeviceState *qd =3D bc->child; > + XScomDevice *xd =3D XSCOM_DEVICE(qd); > + XScomDeviceClass *xc =3D XSCOM_DEVICE_GET_CLASS(xd); > + uint32_t reg[MAX_XSCOM_RANGES * 2]; > + unsigned int i, sz =3D 0; > + void *cp, *p; > + > + /* Some XSCOM slaves may not be represented in the DT */ > + if (!xc->dt_name) { > + continue; > + } > + name =3D g_strdup_printf("%s@%x", xc->dt_name, xd->ranges[0].add= r); > + _FDT((fdt_begin_node(fdt, name))); > + g_free(name); > + for (i =3D 0; i < MAX_XSCOM_RANGES; i++) { > + if (xd->ranges[i].size =3D=3D 0) { > + break; > + } > + reg[sz++] =3D cpu_to_be32(xd->ranges[i].addr); > + reg[sz++] =3D cpu_to_be32(xd->ranges[i].size); > + } > + _FDT((fdt_property(fdt, "reg", reg, sz * 4))); > + if (xc->devnode) { > + _FDT((xc->devnode(xd, fdt))); > + } > +#define MAX_COMPATIBLE_PROP 1024 > + cp =3D p =3D g_malloc0(MAX_COMPATIBLE_PROP); > + i =3D 0; > + while((p - cp) < MAX_COMPATIBLE_PROP) { > + int l; > + if (xc->dt_compatible[i] =3D=3D NULL) { > + break; > + } > + l =3D strlen(xc->dt_compatible[i]); > + if (l >=3D (MAX_COMPATIBLE_PROP - i)) { > + break; > + } > + strcpy(p, xc->dt_compatible[i++]); > + p +=3D l + 1; > + } > + _FDT((fdt_property(fdt, "compatible", cp, p - cp))); > + _FDT((fdt_end_node(fdt))); > + } > + > + _FDT((fdt_end_node(fdt))); > + > + return 0; > +} > + > +static int xscom_qdev_init(DeviceState *qdev) > +{ > + XScomDevice *xdev =3D (XScomDevice *)qdev; > + XScomDeviceClass *xc =3D XSCOM_DEVICE_GET_CLASS(xdev); > + > + if (xc->init) { > + return xc->init(xdev); > + } > + return 0; > +} > + > +static void xscom_device_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *k =3D DEVICE_CLASS(klass); > + k->init =3D xscom_qdev_init; > + k->bus_type =3D TYPE_XSCOM_BUS; > +} > + > +static const TypeInfo xscom_dev_info =3D { > + .name =3D TYPE_XSCOM_DEVICE, > + .parent =3D TYPE_DEVICE, > + .instance_size =3D sizeof(XScomDevice), > + .abstract =3D true, > + .class_size =3D sizeof(XScomDeviceClass), > + .class_init =3D xscom_device_class_init, > +}; > + > +static void xscom_register_types(void) > +{ > + type_register_static(&xscom_info); > + type_register_static(&xscom_bus_info); > + type_register_static(&xscom_dev_info); > +} > + > +type_init(xscom_register_types) > + > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 9a48c16..cb157eb 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -20,10 +20,12 @@ > */ > =20 > #include "hw/hw.h" > +typedef struct XScomBus XScomBus; > =20 > /* Should we turn that into a QOjb of some sort ? */ > typedef struct PnvChip { > uint32_t chip_id; > + XScomBus *xscom; > } PnvChip; > =20 > typedef struct PnvSystem { > diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h > new file mode 100644 > index 0000000..99de078 > --- /dev/null > +++ b/include/hw/ppc/pnv_xscom.h > @@ -0,0 +1,73 @@ > +#ifndef _HW_XSCOM_H > +#define _HW_XSCOM_H > +/* > + * QEMU PowerNV XSCOM bus definitions > + * > + * Copyright (c) 2010 David Gibson, IBM Corporation > + * Based on the s390 virtio bus definitions: > + * Copyright (c) 2009 Alexander Graf > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +#include > + > +#define TYPE_XSCOM_DEVICE "xscom-device" > +#define XSCOM_DEVICE(obj) \ > + OBJECT_CHECK(XScomDevice, (obj), TYPE_XSCOM_DEVICE) > +#define XSCOM_DEVICE_CLASS(klass) \ > + OBJECT_CLASS_CHECK(XScomDeviceClass, (klass), TYPE_XSCOM_DEVICE) > +#define XSCOM_DEVICE_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(XScomDeviceClass, (obj), TYPE_XSCOM_DEVICE) > + > +#define TYPE_XSCOM_BUS "xscom-bus" > +#define XSCOM_BUS(obj) OBJECT_CHECK(XScomBus, (obj), TYPE_XSCOM_BUS) > + > +typedef struct XScomDevice XScomDevice; > +typedef struct XScomBus XScomBus; > + > +typedef struct XScomDeviceClass { > + DeviceClass parent_class; > + > + const char *dt_name; > + const char **dt_compatible; > + int (*init)(XScomDevice *dev); > + int (*devnode)(XScomDevice *dev, void *fdt); > + > + /* Actual XScom accesses */ > + bool (*read)(XScomDevice *dev, uint32_t range, uint32_t offset, uint= 64_t *out_val); > + bool (*write)(XScomDevice *dev, uint32_t range, uint32_t offset, uin= t64_t val); > +} XScomDeviceClass; > + > +typedef struct XScomRange { > + uint32_t addr; > + uint32_t size; > +} XScomRange; > + > +struct XScomDevice { > + DeviceState qdev; > +#define MAX_XSCOM_RANGES 4 > + struct XScomRange ranges[MAX_XSCOM_RANGES]; > +}; > + > +struct XScomBus { > + BusState bus; > + uint32_t chip_id; > +}; > + > +extern void xscom_create(PnvChip *chip); > +extern int xscom_populate_fdt(XScomBus *xscom, void *fdt); > + > + > +#endif /* _HW_XSCOM_H */ --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --doKZ0ri6bHmN2Q5y Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWU9eSAAoJEGw4ysog2bOS2pgQALRPUfRbr89y41EQQK8mm6Th u0LAb3+gdtt/LZ41lKDG3JV4VCYAq1E9DWkJ1VTG0+HnF2SYY20dNzoxptdUnwtB WqyPCH4AKRuTxD2Ohmc+CooV9fblJmhzuvq7rz1HbNbQ3QIQBjVIc0gacmGW5ik5 d4q5Dl0T5qkpuhAP8wteVvYL7Xhrk9Wf/Wnf1CH8RJTpbOxvH/cJX5wf9jHTV9Nd FextJ/HFvN9Rks/Pi02Q+vU3+F7PbOJquiMo3V0M3sum6HfCTkpct83R4g1T8NvW 1TlCN+7yL6V7zs9KqZjdvcW1N1bVCkmpznHnsnYeJI2MqHhkaoaEh6Okmb+SASgw 5c9rjskpnUUiRAbxpVJDUzBEXcYvIuINEwCsRh6PG4667SssxmyHywAvttb2Q6jp g8tBq15dN9FPV1MV66P9wBYYBrs9ln4rTHZKU+tLJIo8nuEt/tOki9MkaWBqlM/F 3BT2Gt1lxb7qV+D2L9rPcET1/j92YSy+Wfe3D0NMdWvrLWLNiCdhkPSNEpO4vs9b O/L61efIx8z3L8Vvvtr80u3fLIOiwRO5cvHfd+mQjX643d9FYUsHaCiP1lRStD9U 39oesBtlSByCbTIDa0K3fi/znVTom77x1ZpNUuLhs3ENN/67MVk9oQohfHWhqK2N YqRsymY9lDHUsrWLXZC1 =tlI0 -----END PGP SIGNATURE----- --doKZ0ri6bHmN2Q5y--