From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38719) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a3eeT-0001us-Nx for qemu-devel@nongnu.org; Tue, 01 Dec 2015 01:43:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a3eeP-000302-CO for qemu-devel@nongnu.org; Tue, 01 Dec 2015 01:43:01 -0500 Date: Tue, 1 Dec 2015 17:43:26 +1100 From: David Gibson Message-ID: <20151201064326.GA4903@voom> References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> <1447201710-10229-42-git-send-email-benh@kernel.crashing.org> <564A7584.5060605@ozlabs.ru> <1447720804.3729.17.camel@kernel.crashing.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="5vNYLRcllDrimb99" Content-Disposition: inline In-Reply-To: <1447720804.3729.17.camel@kernel.crashing.org> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 41/77] ppc/pnv: Add LPC controller and hook it up with a UART and RTC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: Alexey Kardashevskiy , qemu-ppc@nongnu.org, qemu-devel@nongnu.org --5vNYLRcllDrimb99 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Nov 17, 2015 at 11:40:04AM +1100, Benjamin Herrenschmidt wrote: > On Tue, 2015-11-17 at 11:32 +1100, Alexey Kardashevskiy wrote: > > On 11/11/2015 11:27 AM, Benjamin Herrenschmidt wrote: > > > This adds a model of the POWER8 LPC controller. It is then used > > > by the PowerNV code to attach a UART and RTC, which, with the right > > > version of OPAL firmware, will provide a working console. > > >=20 > > > This version of the LPC controller model doesn't yet implement > > > support for the SerIRQ deserializer present in the Naples version > > > of the chip though some preliminary work is there. > > >=20 > >=20 > > Is this LPC controller one per a chip or per a machine? >=20 > Per chip but we usually only wire one up per machine. >=20 > > In general it is quite nice when "-nodefaults" does not create > > neither PHB nor LPC so the user can add them manually with parameters > > different than defaults. >=20 > In this case though, PHB and LPC bridges are all part of the P8 chip, > and I'm trying to represent that topology as best as possible. >=20 > I think "-nodefaults" for Pnv should only be about the devices we > attach to the LPC/PHB not the busses themselves. Exactly what is and isn't covered by -nodefaults is a bit of a mess - part of the topic of my talk at KVM Forum. But on the whole I agree with you, since the LPC is part of the P8 chip, I think it makes sense to include it even with -nodefaults. --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --5vNYLRcllDrimb99 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWXUGOAAoJEGw4ysog2bOSvJAP/j+kq0OpMpvcHj06W31CLBae qyu8YN0gcI9/VQ3dKN1CCDwwUTA6aJWr/vhUv82pFGe4GZGaC63cSaDQaS7FdVGh wxHhetViEyLa1oRBU9p9b3BDkvw9+7jeWYPSo8ms8VA+fVO95x/Ec3tKa1Mh/ETM w4E8IviCCmL3E6v8pDSEUajRjYNgCEAZ7Yz14VddoXdGUrELvA+0IzKr4cX3xPI/ 4G1bHeO9mfQh/1Q1gEWu2MqZgWiupgKMTSbiK9qkV2LMxQHhyMbwGcJkXPtVoYYA XfYVoS9t8nOCvr7dvzi4NQP1O2tQUuqLhJTZC3AHC5athNgYflpVa0YJnAjjIxJo HjIhCuMbI/ZF+9H7kKNJUa81F+wP5Ix2Eto8Cr41tGSWCc+Of+GCc3Kbd368a8pg M+R2Gs1Gf1LX4tQKVUeVd7cz/iu4b+qxLNmtJ8WSjrMednJ2anWO/1o6eC+mqcED +OWjNl4sMFdzUpzJXPg9mNgSKj3O3ki/0yWNCEfVaBzDAnhqGUmLilMuV+/YdxVG abbyVFKz2wPzdOBsdkK0bK5ckPzq/fvw16FD8G3NZ8BXdz7hyhKrPJ+Kjyvs5SCI vtJIcWT77w5IWwBRMuWNiRng+PogLHvseHYnMfxjVMMspwo3JxXr04yGR6ovVbH+ E6myjpKSsa0JmgJT7pKr =xpqE -----END PGP SIGNATURE----- --5vNYLRcllDrimb99--