From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52904) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aJjyP-0005tL-VN for qemu-devel@nongnu.org; Thu, 14 Jan 2016 10:38:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aJjyM-0007Xz-Mi for qemu-devel@nongnu.org; Thu, 14 Jan 2016 10:38:05 -0500 Received: from mx1.redhat.com ([209.132.183.28]:56913) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aJjyM-0007Xk-H9 for qemu-devel@nongnu.org; Thu, 14 Jan 2016 10:38:02 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (Postfix) with ESMTPS id 1EA9F8E90D for ; Thu, 14 Jan 2016 15:38:02 +0000 (UTC) Date: Thu, 14 Jan 2016 17:37:59 +0200 From: "Michael S. Tsirkin" Message-ID: <20160114173718-mutt-send-email-mst@redhat.com> References: <5693D447.8070000@redhat.com> <5693D999.2030504@gmail.com> <5693E349.4090201@redhat.com> <5693EE0B.7030002@redhat.com> <5693F802.2010304@redhat.com> <5693FB2F.2080403@redhat.com> <56979399.20902@redhat.com> <5697B111.6070203@redhat.com> <20160114164309-mutt-send-email-mst@redhat.com> <5697BD6F.7030501@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5697BD6F.7030501@redhat.com> Subject: Re: [Qemu-devel] [PATCH] hw/pci: do not update the PCI mappings while Decode (I/O or memory) bit is not set in the Command register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Marcel Apfelbaum Cc: Laszlo Ersek , qemu-devel@nongnu.org On Thu, Jan 14, 2016 at 05:23:27PM +0200, Marcel Apfelbaum wrote: > On 01/14/2016 04:49 PM, Michael S. Tsirkin wrote: > >On Thu, Jan 14, 2016 at 03:30:41PM +0100, Laszlo Ersek wrote: > >>>2. The same as with pxb, disable Integrated End points for pxb-pcie. > >> > >>My vote, without a doubt. > > > >Yea, me too. > > > > > >On a related note: I wonder whether enough resources will be allocated > >to the bridge to actually make it possible to add devices by hotplug > >later. > > > > It works the same as with PXB, but now instead of having one internal PCI-bridge, > we will have several switches/root ports. Each of them will get the minimum MEM required by > PCI bridges, what does this mean? What if you add a bunch of devices with large memory BARs? They won't fit will they? > however the IO will be allocated only if at least one legacy device > will be present at boot time. (this is at least what SeaBIOS does, I am going to check OVMF actions) > > Also related, checking that PCIe native hotplug works for devices behind > pxb-pcie bridges is my next step after I fix the current issue. > > Thanks, > Marcel > > > > >>> > >>>I am going to look at 1., maybe I is doable in a clean way. > >> > >>My vote: don't. :) > >> > >>Thanks > >>Laszlo > >> > >>>Thanks, > >>>Marcel > >>> > >>> > >>>[...]