From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44132) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLXoC-0005PP-1p for qemu-devel@nongnu.org; Tue, 19 Jan 2016 10:03:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aLXo7-0002Bj-Ns for qemu-devel@nongnu.org; Tue, 19 Jan 2016 10:02:59 -0500 Received: from mail-wm0-x22e.google.com ([2a00:1450:400c:c09::22e]:36870) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLXo7-0002Bf-EX for qemu-devel@nongnu.org; Tue, 19 Jan 2016 10:02:55 -0500 Received: by mail-wm0-x22e.google.com with SMTP id n5so116567934wmn.0 for ; Tue, 19 Jan 2016 07:02:54 -0800 (PST) Date: Tue, 19 Jan 2016 17:02:45 +0200 From: Shmulik Ladkani Message-ID: <20160119170245.5bd72cb2@pixies> In-Reply-To: <569E4797.2080101@gmail.com> References: <1453138550-1096-1-git-send-email-leonid.bloch@ravellosystems.com> <1453138550-1096-5-git-send-email-leonid.bloch@ravellosystems.com> <569E4797.2080101@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC PATCH v2 04/10] pcie: Introduce function for DSN capability creation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Marcel Apfelbaum Cc: "Michael S. Tsirkin" , Leonid Bloch , Jason Wang , Leonid Bloch , qemu-devel@nongnu.org, Dmitry Fleytman Hi Marcel, On Tue, 19 Jan 2016 16:26:31 +0200, marcel.apfelbaum@gmail.com wrote: > > > > +/* DSN */ > > +#define PCI_DSN_VER 1 > > +#define PCI_DSN_SIZEOF 8 > > Are you sure the size of DSN is 8? > Looking at PCIe spec 3, chapter 7.12 I see 12, but I might be wrong. Total size (DSN ext. cap header + Serial Number register) is indeed 12. The Serial Number register itself is 64 bits. Newer qemu already has PCI_EXT_CAP_DSN_SIZEOF defined as 12 (in standard-headers/linux/pci_regs.h) We may choose better naming to reflect the '8 size' refers to the payload.