From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLrf4-0003J3-MF for qemu-devel@nongnu.org; Wed, 20 Jan 2016 07:14:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aLrez-00015O-UK for qemu-devel@nongnu.org; Wed, 20 Jan 2016 07:14:54 -0500 Received: from mail-ob0-x244.google.com ([2607:f8b0:4003:c01::244]:33274) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLrez-00015G-P8 for qemu-devel@nongnu.org; Wed, 20 Jan 2016 07:14:49 -0500 Received: by mail-ob0-x244.google.com with SMTP id oj9so456349obc.0 for ; Wed, 20 Jan 2016 04:14:49 -0800 (PST) Date: Wed, 20 Jan 2016 13:14:44 +0100 From: "Edgar E. Iglesias" Message-ID: <20160120121444.GT29396@toto> References: <1453132414-8127-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1453132414-8127-1-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH] target-arm: Implement FPEXC32_EL2 system register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@linaro.org, qemu-devel@nongnu.org, patches@linaro.org On Mon, Jan 18, 2016 at 03:53:34PM +0000, Peter Maydell wrote: > The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, > and allows those exception levels to read and write the FPEXC > register for a lower exception level that is using AArch32. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > ARM Trusted Firmware expects this to exist (as does your average > hypervisor, I expect). > > target-arm/helper.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 196c111..e8ede3f 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2890,6 +2890,17 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, > tlb_flush(CPU(cpu), 1); > } > > +static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri) > +{ > + if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { > + return CP_ACCESS_TRAP_EL2; > + } > + if (env->cp15.cptr_el[3] & CPTR_TFP) { > + return CP_ACCESS_TRAP_EL3; > + } > + return CP_ACCESS_OK; > +} > + > static const ARMCPRegInfo v8_cp_reginfo[] = { > /* Minimal set of EL0-visible registers. This will need to be expanded > * significantly for system emulation of AArch64 CPUs. > @@ -3150,6 +3161,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, > .type = ARM_CP_NO_RAW, > .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, > + { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, > + .type = ARM_CP_ALIAS, > + .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), > + .access = PL2_RW, .accessfn = fpexc32_access }, > REGINFO_SENTINEL > }; > > -- > 1.9.1 >