From: James Hogan <james.hogan@imgtec.com>
To: Leon Alrae <leon.alrae@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Aurelien Jarno <aurelien@aurel32.net>,
qemu-devel@nongnu.org, kvm@vger.kernel.org
Subject: Re: [Qemu-devel] [PATCH v4 7/7] mips/kvm: Support MSA in MIPS KVM guests
Date: Tue, 2 Feb 2016 12:39:46 +0000 [thread overview]
Message-ID: <20160202123946.GA5038@jhogan-linux.le.imgtec.org> (raw)
In-Reply-To: <56B07DD6.8070203@imgtec.com>
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Hi Leon,
On Tue, Feb 02, 2016 at 09:58:46AM +0000, Leon Alrae wrote:
> Hi James,
>
> On 18/12/15 10:46, James Hogan wrote:
> > @@ -611,17 +664,51 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
> > restore_flush_mode(env);
> > }
> >
> > - /* Floating point registers */
> > - for (i = 0; i < 32; ++i) {
> > - if (env->CP0_Status & (1 << CP0St_FR)) {
> > - err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i),
> > - &env->active_fpu.fpr[i].d);
> > - } else {
> > - err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i),
> > - &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]);
> > + /*
> > + * FPU register state is a subset of MSA vector state, so don't save FPU
> > + * registers if we're emulating a CPU with MSA.
> > + */
> > + if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
> > + /* Floating point registers */
> > + for (i = 0; i < 32; ++i) {
> > + if (env->CP0_Status & (1 << CP0St_FR)) {
> > + err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i),
> > + &env->active_fpu.fpr[i].d);
> > + } else {
> > + err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i),
> > + &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]);
> > + }
> > + if (err < 0) {
> > + DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err);
> > + ret = err;
> > + }
> > }
> > + }
> > + }
> > +
> > + /* Only get MSA state if we're emulating a CPU with MSA */
> > + if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
> > + /* MSA Control Registers */
> > + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR,
> > + &env->msair);
> > + if (err < 0) {
> > + DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err);
> > + ret = err;
> > + }
> > + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR,
> > + &env->active_tc.msacsr);
> > + if (err < 0) {
> > + DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err);
> > + ret = err;
> > + }
>
> Shouldn't MSA's float_status (i.e. msa_fp_status) be restored to reflect
> MSACSR?
Yes, it probably should. Good spot!
I can use restore_msa_fp_status(env); here, and actually the FP one
above (in previous patch) can change to restore_fp_status(env); too,
since it does the same thing.
I've rebased and resolved the uint64 thing too, would you like a resend?
Thanks
James
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next prev parent reply other threads:[~2016-02-02 12:39 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-18 10:45 [Qemu-devel] [PATCH v4 0/7] mips/kvm: Support FPU & SIMD (MSA) in MIPS KVM guests James Hogan
2015-12-18 10:45 ` [Qemu-devel] [PATCH v4 1/7] mips/kvm: Remove a couple of noisy DPRINTFs James Hogan
2015-12-18 10:45 ` [Qemu-devel] [PATCH v4 2/7] mips/kvm: Implement PRid CP0 register James Hogan
2015-12-18 10:46 ` [Qemu-devel] [PATCH v4 3/7] mips/kvm: Implement Config CP0 registers James Hogan
2015-12-18 10:46 ` [Qemu-devel] [PATCH v4 4/7] mips/kvm: Support unsigned KVM registers James Hogan
2015-12-18 10:46 ` [Qemu-devel] [PATCH v4 5/7] mips/kvm: Support signed 64-bit " James Hogan
2015-12-18 10:46 ` [Qemu-devel] [PATCH v4 6/7] mips/kvm: Support FPU in MIPS KVM guests James Hogan
2015-12-18 10:46 ` [Qemu-devel] [PATCH v4 7/7] mips/kvm: Support MSA " James Hogan
2016-02-02 9:58 ` Leon Alrae
2016-02-02 12:39 ` James Hogan [this message]
2016-02-02 13:56 ` Leon Alrae
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